Orange Pi5 kernel

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip USBDP Combo PHY with Samsung IP block

maintainers:
  - Frank Wang <frank.wang@rock-chips.com>
  - Zhang Yubing <yubing.zhang@rock-chips.com>

properties:
  compatible:
    enum:
      - rockchip,rk3588-usbdp-phy

  reg:
    maxItems: 1

  clocks:
    items:
      - description: phy ref clock.
      - description: phy pcs immortal clock.
      - description: phy peripheral clock.

  clock-names:
    items:
      - const: refclk
      - const: immortal
      - const: pclk

  resets:
      - description: phy init reset.
      - description: phy cmn reset.
      - description: phy lane reset.
      - description: phy pcs apb reset.
      - description: phy pma apb reset.

  reset-names:
      - const: init
      - const: cmn
      - const: lane
      - const: pcs_apb
      - const: pma_apb

  rockchip,dp-lane-mux:
    minItems: 2
    maxItems: 4
    description:
      An array of physical Tyep-C lanes indexes. Position of an entry determines
      the dp lane index, while the value of an entry indicater physical Type-C lane.
      The support dp lanes number are 2 or 4. e.g. for 2 lanes dp lanes map, we could
      have "rockchip,dp-lane-mux = <2, 3>;", assuming dp lane0 on Type-C phy lane2,
      dp lane1 on Type-C phy lane3. For 4 lanes dp lanes map, we could have
      "rockchip,dp-lane-mux = <0, 1, 2, 3>;", assuming dp lane0 on Type-C phy lane0,
      dp lane1 on Type-C phy lane1, dp lane2 on Type-C phy lane2, dp lane3 on Type-C
      phy lane3. If dp lane map by DisplayPort Alt mode, this property is not need.

  rockchip,u2phy-grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the 'usb2 phy general register files'.

  rockchip,usb-grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the 'usb general register files'.

  rockchip,usbdpphy-grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the 'usbdp phy general register files'.

  rockchip,vo-grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the 'video output general register files'.
      When select the dp lane mapping will request its phandle.

  dp-port:
    type: object
    additionalProperties: false

    properties:
      "#phy-cells":
        const: 0

    required:
      - "#phy-cells"

  u3-port:
    type: object
    additionalProperties: false

    properties:
      "#phy-cells":
        const: 0

    required:
      - "#phy-cells"

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - dp-port
  - u3-port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3588-cru.h>

    usbdp_phy0: phy@fed80000 {
      compatible = "rockchip,rk3588-usbdp-phy";
      reg = <0x0 0xfed80000 0x0 0x10000>;
      rockchip,u2phy-grf = <&usb2phy0_grf>;
      rockchip,usb-grf = <&usb_grf>;
      rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
      rockchip,vo-grf = <&vo0_grf>;
      clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
               <&cru CLK_USBDP_PHY0_IMMORTAL>,
               <&cru PCLK_USBDPPHY0>;
      clock-names = "refclk", "immortal", "pclk";
      resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
               <&cru SRST_USBDP_COMBO_PHY0_CMN>,
               <&cru SRST_USBDP_COMBO_PHY0_LANE>,
               <&cru SRST_USBDP_COMBO_PHY0_PCS>,
               <&cru SRST_P_USBDPPHY0>;
      reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
      status = "disabled";

      usbdp_phy0_dp: dp-port {
        #phy-cells = <0>;
        status = "disabled";
      };

      usbdp_phy0_u3: u3-port {
        #phy-cells = <0>;
        status = "disabled";
    };