^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: Rockchip USBDP Combo PHY with Samsung IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Frank Wang <frank.wang@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - Zhang Yubing <yubing.zhang@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - rockchip,rk3588-usbdp-phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - description: phy ref clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - description: phy pcs immortal clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - description: phy peripheral clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - const: refclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - const: immortal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - const: pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) resets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - description: phy init reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - description: phy cmn reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - description: phy lane reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - description: phy pcs apb reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - description: phy pma apb reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) reset-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - const: init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - const: cmn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - const: lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - const: pcs_apb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - const: pma_apb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) rockchip,dp-lane-mux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) minItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) maxItems: 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) An array of physical Tyep-C lanes indexes. Position of an entry determines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) the dp lane index, while the value of an entry indicater physical Type-C lane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) The support dp lanes number are 2 or 4. e.g. for 2 lanes dp lanes map, we could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) have "rockchip,dp-lane-mux = <2, 3>;", assuming dp lane0 on Type-C phy lane2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dp lane1 on Type-C phy lane3. For 4 lanes dp lanes map, we could have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "rockchip,dp-lane-mux = <0, 1, 2, 3>;", assuming dp lane0 on Type-C phy lane0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dp lane1 on Type-C phy lane1, dp lane2 on Type-C phy lane2, dp lane3 on Type-C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) phy lane3. If dp lane map by DisplayPort Alt mode, this property is not need.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) rockchip,u2phy-grf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) $ref: /schemas/types.yaml#/definitions/phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) Phandle to the syscon managing the 'usb2 phy general register files'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) rockchip,usb-grf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) $ref: /schemas/types.yaml#/definitions/phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Phandle to the syscon managing the 'usb general register files'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) rockchip,usbdpphy-grf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) $ref: /schemas/types.yaml#/definitions/phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) Phandle to the syscon managing the 'usbdp phy general register files'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) rockchip,vo-grf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) $ref: /schemas/types.yaml#/definitions/phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) Phandle to the syscon managing the 'video output general register files'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) When select the dp lane mapping will request its phandle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dp-port:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) type: object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "#phy-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) - "#phy-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u3-port:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) type: object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "#phy-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) - "#phy-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) - resets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) - reset-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) - dp-port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) - u3-port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #include <dt-bindings/clock/rk3588-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) usbdp_phy0: phy@fed80000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) compatible = "rockchip,rk3588-usbdp-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) reg = <0x0 0xfed80000 0x0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) rockchip,u2phy-grf = <&usb2phy0_grf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) rockchip,usb-grf = <&usb_grf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) rockchip,vo-grf = <&vo0_grf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) <&cru CLK_USBDP_PHY0_IMMORTAL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) <&cru PCLK_USBDPPHY0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) clock-names = "refclk", "immortal", "pclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) <&cru SRST_USBDP_COMBO_PHY0_CMN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) <&cru SRST_USBDP_COMBO_PHY0_LANE>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) <&cru SRST_USBDP_COMBO_PHY0_PCS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) <&cru SRST_P_USBDPPHY0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) usbdp_phy0_dp: dp-port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) usbdp_phy0_u3: u3-port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags