author: andy.hu <andy.hu@starfivetech.com> 2023-05-19 03:34:49 +0000
committer: andy.hu <andy.hu@starfivetech.com> 2023-05-19 03:34:49 +0000
commit: d64059f32b47568913ac1f71096d0734386f2d44
parent: 040cfd685cc90a3b93abf4b035589752ea18f113
Commit Summary:
Diffstat:
1 file changed, 6 insertions, 6 deletions
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index c675e85e19..d02d49797d 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -20,7 +20,7 @@
#size-cells = <0>;
cpu0: cpu@0 {
- compatible = "sifive,u74-mc", "riscv";
+ compatible = "sifive,s7", "riscv";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -35,7 +35,7 @@
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
- riscv,isa = "rv64imacu";
+ riscv,isa = "rv64imacu_zba_zbb";
tlb-split;
status = "disabled";
@@ -62,7 +62,7 @@
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
- riscv,isa = "rv64imafdcbsux";
+ riscv,isa = "rv64imafdcbsux_zba_zbb";
tlb-split;
status = "okay";
@@ -89,7 +89,7 @@
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
- riscv,isa = "rv64imafdcbsux";
+ riscv,isa = "rv64imafdcbsux_zba_zbb";
tlb-split;
status = "okay";
@@ -116,7 +116,7 @@
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
- riscv,isa = "rv64imafdcbsux";
+ riscv,isa = "rv64imafdcbsux_zba_zbb";
tlb-split;
status = "okay";
@@ -143,7 +143,7 @@
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
- riscv,isa = "rv64imafdcbsux";
+ riscv,isa = "rv64imafdcbsux_zba_zbb";
tlb-split;
status = "okay";