VisionFive2 U-Boot

StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

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author: Samin Guo <samin.guo@starfivetech.com> 2023-06-16 11:01:35 +0800 committer: Samin Guo <samin.guo@starfivetech.com> 2023-07-10 11:38:08 +0800 commit: 618eb7825344a7821bc731e94e12766c89529ee7 parent: de7517bdbe830ed5457780f579bcca798419a497
Commit Summary:
borad: starfive: evb: Resize the address space
Diffstat:
1 file changed, 8 insertions, 18 deletions
diff --git a/include/configs/starfive-evb.h b/include/configs/starfive-evb.h
index 362a5fe7de..6d0559f861 100644
--- a/include/configs/starfive-evb.h
+++ b/include/configs/starfive-evb.h
@@ -16,23 +16,22 @@
 #define CONFIG_SPL_MAX_SIZE		0x00040000
 #define CONFIG_SPL_BSS_START_ADDR	0x08040000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x00010000
-#define CONFIG_SYS_SPL_MALLOC_START	(0x80000000)
+#define CONFIG_SYS_SPL_MALLOC_START	0x42000000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x00800000
 
-#define CONFIG_SPL_STACK	(0x08000000 + 0x00180000 -	\
-				 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SPL_STACK		(0x08000000 + 0x00180000 - \
+					GENERATED_GBL_DATA_SIZE)
 
-#define STARFIVE_SPL_BOOT_LOAD_ADDR 0xa0000000
+#define STARFIVE_SPL_BOOT_LOAD_ADDR	0x60000000
 #endif
 
-
 #define CONFIG_SYS_CACHELINE_SIZE 64
 
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
-#define CONFIG_SYS_BOOTM_LEN (32 << 20) /* 32MB */
+#define CONFIG_SYS_BOOTM_LEN	SZ_64M
 
 /*
  * Print Buffer Size
@@ -56,19 +55,13 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		SZ_8M
 
-#define CONFIG_NR_DRAM_BANKS	1
-
-#define PHYS_SDRAM_0		0x40000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_0_SIZE	0x100000000	/* 8 GB */
-
-#define CONFIG_SYS_SDRAM_BASE	(PHYS_SDRAM_0)
-
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
 
 /* Init Stack Pointer */
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_8M)
 
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_16M)
-#define CONFIG_STANDALONE_LOAD_ADDR	0x41000000
+#define CONFIG_STANDALONE_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + SZ_16M)
 
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
@@ -206,11 +199,6 @@
 	BOOTENV						\
 	BOOTENV_SF
 
-/*
- * memtest works on 1.9 MB in DRAM
- */
-#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
-#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
 
 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1		/* allow baudrate change */