author: Samin Guo <samin.guo@starfivetech.com> 2023-04-03 11:39:32 +0800
committer: Samin Guo <samin.guo@starfivetech.com> 2023-04-04 09:33:30 +0800
commit: 41cad11dbfc69454edf03ba0dc8fb05196bd74a8
parent: 5755db49a8814116d2c7eaa7a44c2676e7d566c4
Commit Summary:
Diffstat:
1 file changed, 10 insertions, 0 deletions
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index 21a14bdc4d..e45b6cde3b 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -71,6 +71,16 @@
};
};
+&cachectrl {
+ reg = <0x0 0x2010000 0x0 0x4000>,
+ <0x0 0x2030000 0x0 0x80000>,
+ <0x0 0x8000000 0x0 0x2000000>;
+ reg-names = "control", "prefetcher", "sideband";
+ prefetch-dist-size = <0x4>;
+ prefetch-hart-mask = <0x1e>;
+ prefetch-enable;
+};
+
&uart0 {
clock-frequency = <24000000>;
current-speed = <115200>;