author: Andy Hu <andy.hu@starfivetech.com> 2023-09-01 11:36:27 +0800
committer: Andy Hu <andy.hu@starfivetech.com> 2023-09-01 11:36:27 +0800
commit: d1ff698066686acd73d236b74976972837f2d883
parent: eb60040147458556ecf7c2212074a639dba19c4e
Commit Summary:
Diffstat:
1 file changed, 1 insertion, 1 deletion
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index a2831f719bca..e5d0445767f1 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -635,7 +635,7 @@
clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
<&clkgen JH7110_DMA1P_CLK_AHB>,
<&clkgen JH7110_NOC_BUS_CLK_STG_AXI>;
- clock-names = "core-clk", "cfgr-clk", "stg_clk";
+ clock-names = "core-clk", "cfgr-clk", "noc-clk";
resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
<&rstgen RSTN_U0_DW_DMA1P_AHB>,
<&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;