author: Changhuang Liang <changhuang.liang@starfivetech.com> 2023-06-09 10:56:36 +0800
committer: Changhuang Liang <changhuang.liang@starfivetech.com> 2023-06-19 20:08:18 +0800
commit: 7c67ae19db6b7c5645803b976defeeb3339af7aa
parent: e587e9385148d104d53c8e8ab6ede5ed59386413
Commit Summary:
Diffstat:
3 files changed, 26 insertions, 12 deletions
diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_csi.c b/drivers/media/platform/starfive/v4l2_driver/stf_csi.c
index 254f3c2ba689..9f905d0ed0d8 100644
--- a/drivers/media/platform/starfive/v4l2_driver/stf_csi.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_csi.c
@@ -97,6 +97,7 @@ static int csi_set_stream(struct v4l2_subdev *sd, int enable)
struct v4l2_mbus_framefmt *format;
int ret = 0;
u32 code, width, dt;
+ u8 bpp;
format = __csi_get_format(csi_dev, NULL, STF_CSI_PAD_SINK,
V4L2_SUBDEV_FORMAT_ACTIVE);
@@ -112,20 +113,21 @@ static int csi_set_stream(struct v4l2_subdev *sd, int enable)
return ret;
code = csi_dev->formats_sink[ret].code;
+ bpp = csi_dev->formats_src[ret].bpp;
dt = code_to_data_type(code);
mutex_lock(&csi_dev->stream_lock);
if (enable) {
if (csi_dev->stream_count == 0) {
csi_dev->hw_ops->csi_clk_enable(csi_dev);
- csi_dev->hw_ops->csi_stream_set(csi_dev, enable, dt, width);
+ csi_dev->hw_ops->csi_stream_set(csi_dev, enable, dt, width, bpp);
}
csi_dev->stream_count++;
} else {
if (csi_dev->stream_count == 0)
goto exit;
if (csi_dev->stream_count == 1) {
- csi_dev->hw_ops->csi_stream_set(csi_dev, enable, dt, width);
+ csi_dev->hw_ops->csi_stream_set(csi_dev, enable, dt, width, bpp);
csi_dev->hw_ops->csi_clk_disable(csi_dev);
}
csi_dev->stream_count--;
diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_csi.h b/drivers/media/platform/starfive/v4l2_driver/stf_csi.h
index 5284d3143035..f55b67b7ddba 100644
--- a/drivers/media/platform/starfive/v4l2_driver/stf_csi.h
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_csi.h
@@ -30,9 +30,8 @@ struct csi_hw_ops {
int (*csi_power_on)(struct stf_csi_dev *csi_dev, u8 on);
int (*csi_clk_enable)(struct stf_csi_dev *csi_dev);
int (*csi_clk_disable)(struct stf_csi_dev *csi_dev);
- int (*csi_set_format)(struct stf_csi_dev *csi_dev,
- u32 vsize, u8 bpp, int is_raw10);
- int (*csi_stream_set)(struct stf_csi_dev *csi_dev, int on, u32 dt, u32 width);
+ int (*csi_stream_set)(struct stf_csi_dev *csi_dev, int on,
+ u32 dt, u32 width, u8 bpp);
};
struct stf_csi_dev {
diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
index 4af0ca8119e0..ff8c2f33ad7a 100644
--- a/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
@@ -226,8 +226,28 @@ static void csi2rx_stop(struct stf_csi_dev *csi_dev, void *reg_base)
writel(0, reg_base + CSI2RX_STREAM_CTRL_REG(i));
}
+static void csi_set_vin_axiwr_pix(struct stf_csi_dev *csi_dev, u32 width, u8 bpp)
+{
+ struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
+ u32 value = 0;
+ int cnfg_axiwr_pix_ct = 64 / bpp;
+
+ if (cnfg_axiwr_pix_ct == 2)
+ value = 0;
+ else if (cnfg_axiwr_pix_ct == 4)
+ value = 1;
+ else if (cnfg_axiwr_pix_ct == 8)
+ value = 2;
+
+ reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
+ BIT(14)|BIT(13), value << 13); //u0_vin_cnfg_axiwr0_pix_ct
+ reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
+ BIT(12)|BIT(11)|BIT(10)|BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2),
+ (width / cnfg_axiwr_pix_ct - 1)<<2); //u0_vin_cnfg_axiwr0_pix_cnt_end
+}
+
static int stf_csi_stream_set(struct stf_csi_dev *csi_dev,
- int on, u32 dt, u32 width)
+ int on, u32 dt, u32 width, u8 bpp)
{
struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
void __iomem *reg_base = vin->csi2rx_base;
@@ -237,15 +257,10 @@ static int stf_csi_stream_set(struct stf_csi_dev *csi_dev,
reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20,
BIT(3)|BIT(2)|BIT(1)|BIT(0),
0<<0); //u0_vin_cnfg_axiwr0_channel_sel
- reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
- BIT(14)|BIT(13),
- 1<<13); //u0_vin_cnfg_axiwr0_pix_ct
reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
BIT(16)|BIT(15),
0<<15); //u0_vin_cnfg_axiwr0_pixel_high_bit_sel
- reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
- BIT(12)|BIT(11)|BIT(10)|BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2),
- (width / 4 - 1)<<2); //u0_vin_cnfg_axiwr0_pix_cnt_end
+ csi_set_vin_axiwr_pix(csi_dev, width, bpp);
break;
case SENSOR_ISP:
reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_36,