author: andy.hu <andy.hu@starfivetech.com> 2023-05-17 10:18:06 +0000
committer: andy.hu <andy.hu@starfivetech.com> 2023-05-17 10:18:06 +0000
commit: de486c9fd7b057ee80c69904d6b085c76bea501c
parent: 224175f542e9f537947b58f0c971350f82b80697
Commit Summary:
Diffstat:
1 file changed, 17 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
old mode 100644
new mode 100755
index d7e953b11265..a09e61f8c037
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -44,6 +44,26 @@
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu1>;
+ };
+
+ core1 {
+ cpu = <&cpu2>;
+ };
+
+ core2 {
+ cpu = <&cpu3>;
+ };
+
+ core3 {
+ cpu = <&cpu4>;
+ };
+ };
+ };
+
cpu0: cpu@0 {
compatible = "sifive,u74-mc", "riscv";
reg = <0>;