author: andy.hu <andy.hu@starfivetech.com> 2023-03-03 08:29:50 +0000
committer: andy.hu <andy.hu@starfivetech.com> 2023-03-03 08:29:50 +0000
commit: db67927b31a98d7f93d881c9c4cd94ee60d66808
parent: b95c0e277fb91460c3ac882f7eb99b03d8a64a06
Commit Summary:
Diffstat:
1 file changed, 5 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dts
index cf36ed3e75af..7056854d8d8c 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dts
@@ -200,3 +200,9 @@
pinctrl-0 = <&mclk_ext_pins>;
status = "okay";
};
+
+&cpu1 {
+ cpu-supply = <&cpu_vdd>;
+ clocks = <&clkgen JH7110_CPU_CORE>;
+ clock-names = "cpu";
+};