author: andy.hu <andy.hu@starfivetech.com> 2023-03-09 09:07:55 +0000
committer: andy.hu <andy.hu@starfivetech.com> 2023-03-09 09:07:55 +0000
commit: 8e3822fbc2a779317370ad73e1881cb4d9640c54
parent: ce13d19a52bb8aefc25a390950792d40909308fc
Commit Summary:
Diffstat:
2 files changed, 23 insertions, 3 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 3a0747cd06de..dd0995c9f73f 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/clock/starfive-jh7110-vout.h>
#include <dt-bindings/clock/starfive-jh7110-isp.h>
#include <dt-bindings/power/jh7110-power.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "starfive,jh7110";
@@ -61,6 +62,7 @@
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imac";
tlb-split;
+ #cooling-cells = <2>;
status = "disabled";
cpu0intctrl: interrupt-controller {
@@ -88,6 +90,7 @@
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdc";
tlb-split;
+ #cooling-cells = <2>;
status = "okay";
operating-points-v2 = <&cluster0_opp>;
@@ -116,6 +119,7 @@
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdc";
tlb-split;
+ #cooling-cells = <2>;
status = "okay";
operating-points-v2 = <&cluster0_opp>;
@@ -144,6 +148,7 @@
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdc";
tlb-split;
+ #cooling-cells = <2>;
status = "okay";
operating-points-v2 = <&cluster0_opp>;
@@ -172,6 +177,7 @@
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdc";
tlb-split;
+ #cooling-cells = <2>;
status = "okay";
operating-points-v2 = <&cluster0_opp>;
@@ -641,9 +647,6 @@
thermal-sensors = <&sfctemp>;
- cooling-maps {
- };
-
trips {
cpu_alert0: cpu_alert0 {
/* milliCelsius */
@@ -659,6 +662,16 @@
type = "critical";
};
};
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
diff --git a/arch/riscv/configs/starfive_jh7110_defconfig b/arch/riscv/configs/starfive_jh7110_defconfig
index 201aef8f7a9b..d31249f1d396 100755
--- a/arch/riscv/configs/starfive_jh7110_defconfig
+++ b/arch/riscv/configs/starfive_jh7110_defconfig
@@ -1,3 +1,4 @@
+CONFIG_COMPILE_TEST=y
CONFIG_DEFAULT_HOSTNAME="StarFive"
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
@@ -25,6 +26,7 @@ CONFIG_PM_STD_PARTITION="PARTLABEL=hibernation"
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
CONFIG_PM_TEST_SUSPEND=y
+CONFIG_ENERGY_MODEL=y
CONFIG_CPU_IDLE=y
CONFIG_RISCV_SBI_CPUIDLE=y
# CONFIG_SECCOMP is not set
@@ -139,9 +141,14 @@ CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_SENSORS_SFCTEMP=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_SYSFS=y
CONFIG_STARFIVE_WATCHDOG=y
+# CONFIG_ABX500_CORE is not set
CONFIG_REGULATOR=y
CONFIG_REGULATOR_AXP15060=y
CONFIG_REGULATOR_STARFIVE_JH7110=y