VisionFive2 Linux kernel

StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

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author: ziv.xu <ziv.xu@starfive.com> 2023-04-04 15:59:41 +0800 committer: ziv.xu <ziv.xu@starfive.com> 2023-04-19 17:01:26 +0800 commit: 4b2ff7c386f2249a05f6ac6ade752844f64bdea9 parent: 4dc55a2c338691bb329890fb89495156517d618c
Commit Summary:
spi-cadence-quadspi:modify frequency limit of and set the parent of qspi ref clk
Diffstat:
2 files changed, 14 insertions, 9 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 84d7631a789f..f08aa84bc1e6 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -342,11 +342,13 @@
 			clocks = <&clkgen JH7110_QSPI_CLK_REF>,
 				 <&clkgen JH7110_QSPI_CLK_APB>,
 				 <&clkgen JH7110_AHB1>,
-				 <&clkgen JH7110_QSPI_CLK_AHB>;
+				 <&clkgen JH7110_QSPI_CLK_AHB>,
+				 <&clkgen JH7110_QSPI_REF_SRC>;
 			clock-names = "clk_ref",
 				      "clk_apb",
 				      "ahb1",
-				      "clk_ahb";
+				      "clk_ahb",
+				      "clk_src";
 			resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 				 <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 				 <&rstgen RSTN_U0_CDNS_QSPI_REF>;
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 76d4dc981f39..ff36509fc787 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -45,6 +45,7 @@ enum {
 	CLK_AHB1,
 	CLK_QSPI_AHB,
 	CLK_QSPI_REF,
+	CLK_QSPI_SRC,
 	CLK_QSPI_NUM,
 };
 
@@ -263,12 +264,7 @@ struct cqspi_driver_platdata {
 
 #define CQSPI_IRQ_STATUS_MASK			0x1FFFF
 
-#define CQSPI_DEFAULT_FREQ			2000000
 #define CQSPI_READ_ID_FREQ			1000000
-#define CQSPI_WRITE_DATA_FREQ			12000000
-
-#define STARFIVE_RESET_REG_BASE_ADDR		0x13020000
-#define QSPI_RESET_REG_OFFSET			0x2fc
 
 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
 {
@@ -1229,10 +1225,8 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
 
 	if (op->cmd.opcode == SPINOR_OP_RDID)
 		cqspi_configure(f_pdata, CQSPI_READ_ID_FREQ);
-	else if (op->cmd.opcode == SPINOR_OP_PP_1_1_4)
-		cqspi_configure(f_pdata, CQSPI_WRITE_DATA_FREQ);
 	else
-		cqspi_configure(f_pdata, CQSPI_DEFAULT_FREQ);
+		cqspi_configure(f_pdata, mem->spi->max_speed_hz);
 
 	if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
 		if (!op->addr.nbytes)
@@ -1445,6 +1439,7 @@ static int cadence_quadspi_clk_init(struct platform_device *pdev, struct cqspi_s
 		{ .id = "ahb1" },
 		{ .id = "clk_ahb" },
 		{ .id = "clk_ref" },
+		{ .id = "clk_src" },
 	};
 
 	int ret = 0;
@@ -1459,6 +1454,7 @@ static int cadence_quadspi_clk_init(struct platform_device *pdev, struct cqspi_s
 	cqspi->clks[CLK_AHB1] = qspiclk[1].clk;
 	cqspi->clks[CLK_QSPI_AHB] = qspiclk[2].clk;
 	cqspi->clks[CLK_QSPI_REF] = qspiclk[3].clk;
+	cqspi->clks[CLK_QSPI_SRC] = qspiclk[4].clk;
 
 	ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]);
 	if (ret) {
@@ -1478,6 +1474,12 @@ static int cadence_quadspi_clk_init(struct platform_device *pdev, struct cqspi_s
 		goto disable_ahb1;
 	}
 
+	clk_set_parent(cqspi->clks[CLK_QSPI_REF], cqspi->clks[CLK_QSPI_SRC]);
+	if (ret) {
+		dev_err(&pdev->dev, "%s: failed to set parent of CLK_QSPI_REF\n", __func__);
+		goto disable_ahb_clk;
+	}
+
 	ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_REF]);
 	if (ret) {
 		dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_REF\n", __func__);