Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * intel_pt_decoder.h: Intel Processor Trace support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2013-2014, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef INCLUDE__INTEL_PT_DECODER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define INCLUDE__INTEL_PT_DECODER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <stdint.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <stdbool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "intel-pt-insn-decoder.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define INTEL_PT_IN_TX		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define INTEL_PT_ABORT_TX	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define INTEL_PT_ASYNC		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define INTEL_PT_FUP_IP		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define INTEL_PT_SAMPLE_IPC	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) enum intel_pt_sample_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	INTEL_PT_BRANCH		= 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	INTEL_PT_INSTRUCTION	= 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	INTEL_PT_TRANSACTION	= 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	INTEL_PT_PTW		= 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	INTEL_PT_MWAIT_OP	= 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	INTEL_PT_PWR_ENTRY	= 1 << 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	INTEL_PT_EX_STOP	= 1 << 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	INTEL_PT_PWR_EXIT	= 1 << 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	INTEL_PT_CBR_CHG	= 1 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	INTEL_PT_TRACE_BEGIN	= 1 << 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	INTEL_PT_TRACE_END	= 1 << 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	INTEL_PT_BLK_ITEMS	= 1 << 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) enum intel_pt_period_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	INTEL_PT_PERIOD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	INTEL_PT_PERIOD_INSTRUCTIONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	INTEL_PT_PERIOD_TICKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	INTEL_PT_PERIOD_MTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	INTEL_PT_ERR_NOMEM = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	INTEL_PT_ERR_INTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	INTEL_PT_ERR_BADPKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	INTEL_PT_ERR_NODATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	INTEL_PT_ERR_NOINSN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	INTEL_PT_ERR_MISMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	INTEL_PT_ERR_OVR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	INTEL_PT_ERR_LOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	INTEL_PT_ERR_UNK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	INTEL_PT_ERR_NELOOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	INTEL_PT_ERR_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) enum intel_pt_param_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * FUP packet can contain next linear instruction pointer instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * current linear instruction pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	INTEL_PT_FUP_WITH_NLIP	= 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) enum intel_pt_blk_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	INTEL_PT_GP_REGS	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	INTEL_PT_PEBS_BASIC	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	INTEL_PT_PEBS_MEM	= 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	INTEL_PT_LBR_0		= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	INTEL_PT_LBR_1		= 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	INTEL_PT_LBR_2		= 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	INTEL_PT_XMM		= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	INTEL_PT_BLK_TYPE_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * The block type numbers are not sequential but here they are given sequential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * positions to avoid wasting space for array placement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) enum intel_pt_blk_type_pos {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	INTEL_PT_GP_REGS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	INTEL_PT_PEBS_BASIC_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	INTEL_PT_PEBS_MEM_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	INTEL_PT_LBR_0_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	INTEL_PT_LBR_1_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	INTEL_PT_LBR_2_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	INTEL_PT_XMM_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	INTEL_PT_BLK_TYPE_CNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* Get the array position for a block type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static inline int intel_pt_blk_type_pos(enum intel_pt_blk_type blk_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define BLK_TYPE(bt) [INTEL_PT_##bt] = INTEL_PT_##bt##_POS + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	const int map[INTEL_PT_BLK_TYPE_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		BLK_TYPE(GP_REGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		BLK_TYPE(PEBS_BASIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		BLK_TYPE(PEBS_MEM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		BLK_TYPE(LBR_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		BLK_TYPE(LBR_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		BLK_TYPE(LBR_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		BLK_TYPE(XMM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #undef BLK_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return blk_type < INTEL_PT_BLK_TYPE_MAX ? map[blk_type] - 1 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define INTEL_PT_BLK_ITEM_ID_CNT	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * Use unions so that the block items can be accessed by name or by array index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * There is an array of 32-bit masks for each block type, which indicate which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * values are present. Then arrays of 32 64-bit values for each block type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct intel_pt_blk_items {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		uint32_t mask[INTEL_PT_BLK_TYPE_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			uint32_t has_rflags:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			uint32_t has_rip:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			uint32_t has_rax:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			uint32_t has_rcx:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			uint32_t has_rdx:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			uint32_t has_rbx:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			uint32_t has_rsp:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			uint32_t has_rbp:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			uint32_t has_rsi:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			uint32_t has_rdi:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			uint32_t has_r8:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			uint32_t has_r9:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			uint32_t has_r10:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			uint32_t has_r11:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			uint32_t has_r12:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			uint32_t has_r13:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			uint32_t has_r14:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			uint32_t has_r15:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			uint32_t has_unused_0:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			uint32_t has_ip:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			uint32_t has_applicable_counters:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			uint32_t has_timestamp:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			uint32_t has_unused_1:29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			uint32_t has_mem_access_address:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			uint32_t has_mem_aux_info:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			uint32_t has_mem_access_latency:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			uint32_t has_tsx_aux_info:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			uint32_t has_unused_2:28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			uint32_t has_lbr_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			uint32_t has_lbr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			uint32_t has_lbr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			uint32_t has_xmm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		uint64_t val[INTEL_PT_BLK_TYPE_CNT][INTEL_PT_BLK_ITEM_ID_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				uint64_t rflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				uint64_t rip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				uint64_t rax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				uint64_t rcx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				uint64_t rdx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				uint64_t rbx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				uint64_t rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				uint64_t rbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				uint64_t rsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				uint64_t rdi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				uint64_t r8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				uint64_t r9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				uint64_t r10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				uint64_t r11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				uint64_t r12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				uint64_t r13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				uint64_t r14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				uint64_t r15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				uint64_t unused_0[INTEL_PT_BLK_ITEM_ID_CNT - 18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 				uint64_t ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 				uint64_t applicable_counters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				uint64_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 				uint64_t unused_1[INTEL_PT_BLK_ITEM_ID_CNT - 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				uint64_t mem_access_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 				uint64_t mem_aux_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				uint64_t mem_access_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				uint64_t tsx_aux_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				uint64_t unused_2[INTEL_PT_BLK_ITEM_ID_CNT - 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			uint64_t lbr_0[INTEL_PT_BLK_ITEM_ID_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			uint64_t lbr_1[INTEL_PT_BLK_ITEM_ID_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			uint64_t lbr_2[INTEL_PT_BLK_ITEM_ID_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			uint64_t xmm[INTEL_PT_BLK_ITEM_ID_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	bool is_32_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct intel_pt_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	enum intel_pt_sample_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	uint64_t from_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	uint64_t to_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	uint64_t cr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	uint64_t tot_insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	uint64_t tot_cyc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	uint64_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	uint64_t est_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	uint64_t trace_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	uint64_t ptw_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	uint64_t mwait_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	uint64_t pwre_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	uint64_t pwrx_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	uint64_t cbr_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	uint32_t cbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	uint32_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	enum intel_pt_insn_op insn_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	int insn_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	char insn[INTEL_PT_INSN_BUF_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct intel_pt_blk_items items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct intel_pt_insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct intel_pt_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	const unsigned char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	bool consecutive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	uint64_t ref_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	uint64_t trace_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) typedef int (*intel_pt_lookahead_cb_t)(struct intel_pt_buffer *, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct intel_pt_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	int (*get_trace)(struct intel_pt_buffer *buffer, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	int (*walk_insn)(struct intel_pt_insn *intel_pt_insn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			 uint64_t *insn_cnt_ptr, uint64_t *ip, uint64_t to_ip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			 uint64_t max_insn_cnt, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	bool (*pgd_ip)(uint64_t ip, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	int (*lookahead)(void *data, intel_pt_lookahead_cb_t cb, void *cb_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	bool return_compression;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	bool branch_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	uint64_t ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	uint64_t period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	enum intel_pt_period_type period_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	unsigned max_non_turbo_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	unsigned int mtc_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	uint32_t tsc_ctc_ratio_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	uint32_t tsc_ctc_ratio_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	enum intel_pt_param_flags flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	unsigned int quick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct intel_pt_decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct intel_pt_decoder *intel_pt_decoder_new(struct intel_pt_params *params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) void intel_pt_decoder_free(struct intel_pt_decoder *decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) const struct intel_pt_state *intel_pt_decode(struct intel_pt_decoder *decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int intel_pt_fast_forward(struct intel_pt_decoder *decoder, uint64_t timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned char *intel_pt_find_overlap(unsigned char *buf_a, size_t len_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 				     unsigned char *buf_b, size_t len_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 				     bool have_tsc, bool *consecutive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int intel_pt__strerror(int code, char *buf, size_t buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #endif