^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * intel_pt_decoder.c: Intel Processor Trace support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2013-2014, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _GNU_SOURCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _GNU_SOURCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <stdlib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <stdbool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <stdint.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <inttypes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/zalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "../auxtrace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "intel-pt-insn-decoder.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "intel-pt-pkt-decoder.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "intel-pt-decoder.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "intel-pt-log.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BITULL(x) (1ULL << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* IA32_RTIT_CTL MSR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define INTEL_PT_CYC_ENABLE BITULL(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define INTEL_PT_CYC_THRESHOLD (BITULL(22) | BITULL(21) | BITULL(20) | BITULL(19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define INTEL_PT_CYC_THRESHOLD_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define INTEL_PT_BLK_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BIT63 (((uint64_t)1 << 63))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define INTEL_PT_RETURN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Maximum number of loops with no packets consumed i.e. stuck in a loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define INTEL_PT_MAX_LOOPS 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct intel_pt_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct intel_pt_blk *prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) uint64_t ip[INTEL_PT_BLK_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct intel_pt_stack {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct intel_pt_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct intel_pt_blk *spare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enum intel_pt_pkt_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) INTEL_PT_STATE_NO_PSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) INTEL_PT_STATE_NO_IP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) INTEL_PT_STATE_ERR_RESYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) INTEL_PT_STATE_IN_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) INTEL_PT_STATE_TNT_CONT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) INTEL_PT_STATE_TNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) INTEL_PT_STATE_TIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) INTEL_PT_STATE_TIP_PGD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) INTEL_PT_STATE_FUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) INTEL_PT_STATE_FUP_NO_TIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) INTEL_PT_STATE_RESAMPLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static inline bool intel_pt_sample_time(enum intel_pt_pkt_state pkt_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) switch (pkt_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case INTEL_PT_STATE_NO_PSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case INTEL_PT_STATE_NO_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) case INTEL_PT_STATE_ERR_RESYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case INTEL_PT_STATE_IN_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case INTEL_PT_STATE_TNT_CONT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case INTEL_PT_STATE_RESAMPLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case INTEL_PT_STATE_TNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case INTEL_PT_STATE_TIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case INTEL_PT_STATE_TIP_PGD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case INTEL_PT_STATE_FUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case INTEL_PT_STATE_FUP_NO_TIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #ifdef INTEL_PT_STRICT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define INTEL_PT_STATE_ERR1 INTEL_PT_STATE_NO_PSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define INTEL_PT_STATE_ERR2 INTEL_PT_STATE_NO_PSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define INTEL_PT_STATE_ERR3 INTEL_PT_STATE_NO_PSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define INTEL_PT_STATE_ERR4 INTEL_PT_STATE_NO_PSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define INTEL_PT_STATE_ERR1 (decoder->pkt_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define INTEL_PT_STATE_ERR2 INTEL_PT_STATE_NO_IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define INTEL_PT_STATE_ERR3 INTEL_PT_STATE_ERR_RESYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define INTEL_PT_STATE_ERR4 INTEL_PT_STATE_IN_SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct intel_pt_decoder {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int (*get_trace)(struct intel_pt_buffer *buffer, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int (*walk_insn)(struct intel_pt_insn *intel_pt_insn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) uint64_t *insn_cnt_ptr, uint64_t *ip, uint64_t to_ip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) uint64_t max_insn_cnt, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) bool (*pgd_ip)(uint64_t ip, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int (*lookahead)(void *data, intel_pt_lookahead_cb_t cb, void *cb_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct intel_pt_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const unsigned char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) bool return_compression;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bool branch_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bool mtc_insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bool pge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) bool have_tma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bool have_cyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) bool fixup_last_mtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) bool have_last_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bool in_psb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) bool hop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bool hop_psb_fup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bool leap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enum intel_pt_param_flags flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) uint64_t pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) uint64_t last_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) uint64_t ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) uint64_t cr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uint64_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) uint64_t tsc_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) uint64_t ref_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) uint64_t buf_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) uint64_t sample_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) uint64_t ret_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) uint64_t ctc_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) uint64_t ctc_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) uint64_t cycle_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) uint64_t cyc_ref_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) uint32_t last_mtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) uint32_t tsc_ctc_ratio_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) uint32_t tsc_ctc_ratio_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) uint32_t tsc_ctc_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) uint32_t tsc_slip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) uint32_t ctc_rem_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int mtc_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct intel_pt_stack stack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) enum intel_pt_pkt_state pkt_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) enum intel_pt_pkt_ctx pkt_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) enum intel_pt_pkt_ctx prev_pkt_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) enum intel_pt_blk_type blk_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int blk_type_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct intel_pt_pkt packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct intel_pt_pkt tnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int pkt_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int last_packet_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int cbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int cbr_seen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int max_non_turbo_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) double max_non_turbo_ratio_fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) double cbr_cyc_to_tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) double calc_cyc_to_tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bool have_calc_cyc_to_tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int exec_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int insn_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) uint64_t period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) enum intel_pt_period_type period_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) uint64_t tot_insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) uint64_t period_insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) uint64_t period_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) uint64_t period_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) uint64_t last_masked_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) uint64_t tot_cyc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) uint64_t sample_tot_cyc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) uint64_t base_cyc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) uint64_t cyc_cnt_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) uint64_t ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) uint64_t cyc_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) double tsc_to_cyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bool continuous_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bool overflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) bool set_fup_tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) bool set_fup_ptw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) bool set_fup_mwait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bool set_fup_pwre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bool set_fup_exstop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) bool set_fup_bep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) bool sample_cyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int fup_tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) uint64_t fup_ptw_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) uint64_t fup_mwait_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) uint64_t fup_pwre_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) uint64_t cbr_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) uint64_t timestamp_insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) uint64_t sample_insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) uint64_t stuck_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int no_progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int stuck_ip_prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int stuck_ip_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) const unsigned char *next_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) size_t next_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned char temp_buf[INTEL_PT_PKT_MAX_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static uint64_t intel_pt_lower_power_of_2(uint64_t x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) for (i = 0; x != 1; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) x >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return x << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static uint64_t intel_pt_cyc_threshold(uint64_t ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!(ctl & INTEL_PT_CYC_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return (ctl & INTEL_PT_CYC_THRESHOLD) >> INTEL_PT_CYC_THRESHOLD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void intel_pt_setup_period(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (decoder->period_type == INTEL_PT_PERIOD_TICKS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) uint64_t period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) period = intel_pt_lower_power_of_2(decoder->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) decoder->period_mask = ~(period - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) decoder->period_ticks = period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static uint64_t multdiv(uint64_t t, uint32_t n, uint32_t d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return (t / d) * n + ((t % d) * n) / d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct intel_pt_decoder *intel_pt_decoder_new(struct intel_pt_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct intel_pt_decoder *decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!params->get_trace || !params->walk_insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) decoder = zalloc(sizeof(struct intel_pt_decoder));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (!decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) decoder->get_trace = params->get_trace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) decoder->walk_insn = params->walk_insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) decoder->pgd_ip = params->pgd_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) decoder->lookahead = params->lookahead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) decoder->data = params->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) decoder->return_compression = params->return_compression;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) decoder->branch_enable = params->branch_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) decoder->hop = params->quick >= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) decoder->leap = params->quick >= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) decoder->flags = params->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) decoder->ctl = params->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) decoder->period = params->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) decoder->period_type = params->period_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) decoder->max_non_turbo_ratio = params->max_non_turbo_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) decoder->max_non_turbo_ratio_fp = params->max_non_turbo_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) decoder->cyc_threshold = intel_pt_cyc_threshold(decoder->ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) intel_pt_setup_period(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) decoder->mtc_shift = params->mtc_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) decoder->ctc_rem_mask = (1 << decoder->mtc_shift) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) decoder->tsc_ctc_ratio_n = params->tsc_ctc_ratio_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) decoder->tsc_ctc_ratio_d = params->tsc_ctc_ratio_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (!decoder->tsc_ctc_ratio_n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) decoder->tsc_ctc_ratio_d = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (decoder->tsc_ctc_ratio_d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!(decoder->tsc_ctc_ratio_n % decoder->tsc_ctc_ratio_d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) decoder->tsc_ctc_mult = decoder->tsc_ctc_ratio_n /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) decoder->tsc_ctc_ratio_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * A TSC packet can slip past MTC packets so that the timestamp appears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * to go backwards. One estimate is that can be up to about 40 CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * cycles, which is certainly less than 0x1000 TSC ticks, but accept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * slippage an order of magnitude more to be on the safe side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) decoder->tsc_slip = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) intel_pt_log("timestamp: mtc_shift %u\n", decoder->mtc_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) intel_pt_log("timestamp: tsc_ctc_ratio_n %u\n", decoder->tsc_ctc_ratio_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) intel_pt_log("timestamp: tsc_ctc_ratio_d %u\n", decoder->tsc_ctc_ratio_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) intel_pt_log("timestamp: tsc_ctc_mult %u\n", decoder->tsc_ctc_mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) intel_pt_log("timestamp: tsc_slip %#x\n", decoder->tsc_slip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (decoder->hop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) intel_pt_log("Hop mode: decoding FUP and TIPs, but not TNT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void intel_pt_pop_blk(struct intel_pt_stack *stack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct intel_pt_blk *blk = stack->blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) stack->blk = blk->prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (!stack->spare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) stack->spare = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) free(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static uint64_t intel_pt_pop(struct intel_pt_stack *stack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!stack->pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!stack->blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) intel_pt_pop_blk(stack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!stack->blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) stack->pos = INTEL_PT_BLK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return stack->blk->ip[--stack->pos];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int intel_pt_alloc_blk(struct intel_pt_stack *stack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct intel_pt_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (stack->spare) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) blk = stack->spare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) stack->spare = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) blk = malloc(sizeof(struct intel_pt_blk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) blk->prev = stack->blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) stack->blk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) stack->pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int intel_pt_push(struct intel_pt_stack *stack, uint64_t ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!stack->blk || stack->pos == INTEL_PT_BLK_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) err = intel_pt_alloc_blk(stack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) stack->blk->ip[stack->pos++] = ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void intel_pt_clear_stack(struct intel_pt_stack *stack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) while (stack->blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) intel_pt_pop_blk(stack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) stack->pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void intel_pt_free_stack(struct intel_pt_stack *stack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) intel_pt_clear_stack(stack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) zfree(&stack->blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) zfree(&stack->spare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) void intel_pt_decoder_free(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) intel_pt_free_stack(&decoder->stack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) free(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int intel_pt_ext_err(int code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) switch (code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case -ENOMEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return INTEL_PT_ERR_NOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case -ENOSYS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return INTEL_PT_ERR_INTERN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case -EBADMSG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return INTEL_PT_ERR_BADPKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case -ENODATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return INTEL_PT_ERR_NODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case -EILSEQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return INTEL_PT_ERR_NOINSN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case -ENOENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return INTEL_PT_ERR_MISMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case -EOVERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return INTEL_PT_ERR_OVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case -ENOSPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return INTEL_PT_ERR_LOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case -ELOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return INTEL_PT_ERR_NELOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return INTEL_PT_ERR_UNK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const char *intel_pt_err_msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) [INTEL_PT_ERR_NOMEM] = "Memory allocation failed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [INTEL_PT_ERR_INTERN] = "Internal error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) [INTEL_PT_ERR_BADPKT] = "Bad packet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) [INTEL_PT_ERR_NODATA] = "No more data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [INTEL_PT_ERR_NOINSN] = "Failed to get instruction",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) [INTEL_PT_ERR_MISMAT] = "Trace doesn't match instruction",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) [INTEL_PT_ERR_OVR] = "Overflow packet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) [INTEL_PT_ERR_LOST] = "Lost trace data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) [INTEL_PT_ERR_UNK] = "Unknown error!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [INTEL_PT_ERR_NELOOP] = "Never-ending loop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int intel_pt__strerror(int code, char *buf, size_t buflen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (code < 1 || code >= INTEL_PT_ERR_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) code = INTEL_PT_ERR_UNK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) strlcpy(buf, intel_pt_err_msgs[code], buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static uint64_t intel_pt_calc_ip(const struct intel_pt_pkt *packet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) uint64_t last_ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) uint64_t ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) switch (packet->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ip = (last_ip & (uint64_t)0xffffffffffff0000ULL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) packet->payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ip = (last_ip & (uint64_t)0xffffffff00000000ULL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) packet->payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ip = packet->payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Sign-extend 6-byte ip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (ip & (uint64_t)0x800000000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ip |= (uint64_t)0xffff000000000000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ip = (last_ip & (uint64_t)0xffff000000000000ULL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) packet->payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ip = packet->payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static inline void intel_pt_set_last_ip(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) decoder->last_ip = intel_pt_calc_ip(&decoder->packet, decoder->last_ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) decoder->have_last_ip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static inline void intel_pt_set_ip(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) intel_pt_set_last_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) decoder->ip = decoder->last_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void intel_pt_decoder_log_packet(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) intel_pt_log_packet(&decoder->packet, decoder->pkt_len, decoder->pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) decoder->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int intel_pt_bug(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) intel_pt_log("ERROR: Internal error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) decoder->pkt_state = INTEL_PT_STATE_NO_PSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static inline void intel_pt_clear_tx_flags(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) decoder->tx_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static inline void intel_pt_update_in_tx(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) decoder->tx_flags = decoder->packet.payload & INTEL_PT_IN_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int intel_pt_bad_packet(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) intel_pt_clear_tx_flags(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) decoder->have_tma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) decoder->pkt_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) decoder->pkt_step = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) intel_pt_decoder_log_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (decoder->pkt_state != INTEL_PT_STATE_NO_PSB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) intel_pt_log("ERROR: Bad packet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) decoder->pkt_state = INTEL_PT_STATE_ERR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static inline void intel_pt_update_sample_time(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) decoder->sample_timestamp = decoder->timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) decoder->sample_insn_cnt = decoder->timestamp_insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static void intel_pt_reposition(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) decoder->ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) decoder->pkt_state = INTEL_PT_STATE_NO_PSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) decoder->timestamp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) decoder->have_tma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int intel_pt_get_data(struct intel_pt_decoder *decoder, bool reposition)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct intel_pt_buffer buffer = { .buf = 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) decoder->pkt_step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) intel_pt_log("Getting more data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ret = decoder->get_trace(&buffer, decoder->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) decoder->buf = buffer.buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) decoder->len = buffer.len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!decoder->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) intel_pt_log("No more data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) decoder->buf_timestamp = buffer.ref_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (!buffer.consecutive || reposition) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) intel_pt_reposition(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) decoder->ref_timestamp = buffer.ref_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) decoder->state.trace_nr = buffer.trace_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) intel_pt_log("Reference timestamp 0x%" PRIx64 "\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) decoder->ref_timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return -ENOLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int intel_pt_get_next_data(struct intel_pt_decoder *decoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) bool reposition)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!decoder->next_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return intel_pt_get_data(decoder, reposition);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) decoder->buf = decoder->next_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) decoder->len = decoder->next_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) decoder->next_buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) decoder->next_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int intel_pt_get_split_packet(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned char *buf = decoder->temp_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) size_t old_len, len, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) old_len = decoder->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) len = decoder->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) memcpy(buf, decoder->buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ret = intel_pt_get_data(decoder, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) decoder->pos += old_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret < 0 ? ret : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) n = INTEL_PT_PKT_MAX_SZ - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (n > decoder->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) n = decoder->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) memcpy(buf + len, decoder->buf, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) len += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) decoder->prev_pkt_ctx = decoder->pkt_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = intel_pt_get_packet(buf, len, &decoder->packet, &decoder->pkt_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (ret < (int)old_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) decoder->next_buf = decoder->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) decoder->next_len = decoder->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) decoder->buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) decoder->len = old_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return intel_pt_bad_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) decoder->next_buf = decoder->buf + (ret - old_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) decoder->next_len = decoder->len - (ret - old_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) decoder->buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) decoder->len = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct intel_pt_pkt_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct intel_pt_decoder *decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct intel_pt_pkt packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) uint64_t pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int last_packet_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) typedef int (*intel_pt_pkt_cb_t)(struct intel_pt_pkt_info *pkt_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Lookahead packets in current buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static int intel_pt_pkt_lookahead(struct intel_pt_decoder *decoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) intel_pt_pkt_cb_t cb, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct intel_pt_pkt_info pkt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) const unsigned char *buf = decoder->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) enum intel_pt_pkt_ctx pkt_ctx = decoder->pkt_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) size_t len = decoder->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pkt_info.decoder = decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pkt_info.pos = decoder->pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) pkt_info.pkt_len = decoder->pkt_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) pkt_info.last_packet_type = decoder->last_packet_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) pkt_info.data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) pkt_info.pos += pkt_info.pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) buf += pkt_info.pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) len -= pkt_info.pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return INTEL_PT_NEED_MORE_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret = intel_pt_get_packet(buf, len, &pkt_info.packet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) &pkt_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return INTEL_PT_NEED_MORE_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) pkt_info.pkt_len = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) } while (pkt_info.packet.type == INTEL_PT_PAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret = cb(&pkt_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) pkt_info.last_packet_type = pkt_info.packet.type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct intel_pt_calc_cyc_to_tsc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) uint64_t cycle_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) unsigned int cbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) uint32_t last_mtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) uint64_t ctc_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) uint64_t ctc_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) uint64_t tsc_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) uint64_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) bool have_tma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) bool fixup_last_mtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) bool from_mtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) double cbr_cyc_to_tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * MTC provides a 8-bit slice of CTC but the TMA packet only provides the lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * 16 bits of CTC. If mtc_shift > 8 then some of the MTC bits are not in the CTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * provided by the TMA packet. Fix-up the last_mtc calculated from the TMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * packet by copying the missing bits from the current MTC assuming the least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * difference between the two, and that the current MTC comes after last_mtc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static void intel_pt_fixup_last_mtc(uint32_t mtc, int mtc_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) uint32_t *last_mtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) uint32_t first_missing_bit = 1U << (16 - mtc_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) uint32_t mask = ~(first_missing_bit - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) *last_mtc |= mtc & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (*last_mtc >= mtc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) *last_mtc -= first_missing_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *last_mtc &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static int intel_pt_calc_cyc_cb(struct intel_pt_pkt_info *pkt_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct intel_pt_decoder *decoder = pkt_info->decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct intel_pt_calc_cyc_to_tsc_info *data = pkt_info->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) uint64_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) double cyc_to_tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) unsigned int cbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) uint32_t mtc, mtc_delta, ctc, fc, ctc_rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) switch (pkt_info->packet.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) case INTEL_PT_TNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case INTEL_PT_TIP_PGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) case INTEL_PT_TIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) case INTEL_PT_FUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) case INTEL_PT_PSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) case INTEL_PT_PIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) case INTEL_PT_MODE_EXEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case INTEL_PT_MODE_TSX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) case INTEL_PT_PSBEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) case INTEL_PT_PAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) case INTEL_PT_VMCS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) case INTEL_PT_MNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) case INTEL_PT_PTWRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) case INTEL_PT_PTWRITE_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) case INTEL_PT_BBP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) case INTEL_PT_BIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) case INTEL_PT_BEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) case INTEL_PT_BEP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case INTEL_PT_MTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (!data->have_tma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) mtc = pkt_info->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (decoder->mtc_shift > 8 && data->fixup_last_mtc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) data->fixup_last_mtc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) intel_pt_fixup_last_mtc(mtc, decoder->mtc_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) &data->last_mtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (mtc > data->last_mtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) mtc_delta = mtc - data->last_mtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) mtc_delta = mtc + 256 - data->last_mtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) data->ctc_delta += mtc_delta << decoder->mtc_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) data->last_mtc = mtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (decoder->tsc_ctc_mult) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) timestamp = data->ctc_timestamp +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) data->ctc_delta * decoder->tsc_ctc_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) timestamp = data->ctc_timestamp +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) multdiv(data->ctc_delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) decoder->tsc_ctc_ratio_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) decoder->tsc_ctc_ratio_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (timestamp < data->timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (pkt_info->last_packet_type != INTEL_PT_CYC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) data->timestamp = timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) case INTEL_PT_TSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * For now, do not support using TSC packets - refer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * intel_pt_calc_cyc_to_tsc().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (data->from_mtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) timestamp = pkt_info->packet.payload |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) (data->timestamp & (0xffULL << 56));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (data->from_mtc && timestamp < data->timestamp &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) data->timestamp - timestamp < decoder->tsc_slip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (timestamp < data->timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) timestamp += (1ULL << 56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (pkt_info->last_packet_type != INTEL_PT_CYC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (data->from_mtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) data->tsc_timestamp = timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) data->timestamp = timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) case INTEL_PT_TMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (data->from_mtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!decoder->tsc_ctc_ratio_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ctc = pkt_info->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) fc = pkt_info->packet.count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ctc_rem = ctc & decoder->ctc_rem_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) data->last_mtc = (ctc >> decoder->mtc_shift) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) data->ctc_timestamp = data->tsc_timestamp - fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (decoder->tsc_ctc_mult) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) data->ctc_timestamp -= ctc_rem * decoder->tsc_ctc_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) data->ctc_timestamp -=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) multdiv(ctc_rem, decoder->tsc_ctc_ratio_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) decoder->tsc_ctc_ratio_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) data->ctc_delta = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) data->have_tma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) data->fixup_last_mtc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) case INTEL_PT_CYC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) data->cycle_cnt += pkt_info->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) case INTEL_PT_CBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) cbr = pkt_info->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (data->cbr && data->cbr != cbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) data->cbr = cbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) data->cbr_cyc_to_tsc = decoder->max_non_turbo_ratio_fp / cbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) case INTEL_PT_TIP_PGD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case INTEL_PT_TRACESTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) case INTEL_PT_EXSTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case INTEL_PT_EXSTOP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) case INTEL_PT_MWAIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) case INTEL_PT_PWRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case INTEL_PT_PWRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) case INTEL_PT_OVF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) case INTEL_PT_BAD: /* Does not happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (!data->cbr && decoder->cbr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) data->cbr = decoder->cbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) data->cbr_cyc_to_tsc = decoder->cbr_cyc_to_tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (!data->cycle_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) cyc_to_tsc = (double)(timestamp - decoder->timestamp) / data->cycle_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (data->cbr && cyc_to_tsc > data->cbr_cyc_to_tsc &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) cyc_to_tsc / data->cbr_cyc_to_tsc > 1.25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) intel_pt_log("Timestamp: calculated %g TSC ticks per cycle too big (c.f. CBR-based value %g), pos " x64_fmt "\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) cyc_to_tsc, data->cbr_cyc_to_tsc, pkt_info->pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) decoder->calc_cyc_to_tsc = cyc_to_tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) decoder->have_calc_cyc_to_tsc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (data->cbr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) intel_pt_log("Timestamp: calculated %g TSC ticks per cycle c.f. CBR-based value %g, pos " x64_fmt "\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) cyc_to_tsc, data->cbr_cyc_to_tsc, pkt_info->pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) intel_pt_log("Timestamp: calculated %g TSC ticks per cycle c.f. unknown CBR-based value, pos " x64_fmt "\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) cyc_to_tsc, pkt_info->pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static void intel_pt_calc_cyc_to_tsc(struct intel_pt_decoder *decoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) bool from_mtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct intel_pt_calc_cyc_to_tsc_info data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .cycle_cnt = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .cbr = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .last_mtc = decoder->last_mtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .ctc_timestamp = decoder->ctc_timestamp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .ctc_delta = decoder->ctc_delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .tsc_timestamp = decoder->tsc_timestamp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .timestamp = decoder->timestamp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .have_tma = decoder->have_tma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .fixup_last_mtc = decoder->fixup_last_mtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .from_mtc = from_mtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .cbr_cyc_to_tsc = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * For now, do not support using TSC packets for at least the reasons:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * 1) timing might have stopped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * 2) TSC packets within PSB+ can slip against CYC packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (!from_mtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) intel_pt_pkt_lookahead(decoder, intel_pt_calc_cyc_cb, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static int intel_pt_get_next_packet(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) decoder->last_packet_type = decoder->packet.type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) decoder->pos += decoder->pkt_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) decoder->buf += decoder->pkt_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) decoder->len -= decoder->pkt_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (!decoder->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ret = intel_pt_get_next_data(decoder, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) decoder->prev_pkt_ctx = decoder->pkt_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ret = intel_pt_get_packet(decoder->buf, decoder->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) &decoder->packet, &decoder->pkt_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (ret == INTEL_PT_NEED_MORE_BYTES && BITS_PER_LONG == 32 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) decoder->len < INTEL_PT_PKT_MAX_SZ && !decoder->next_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ret = intel_pt_get_split_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return intel_pt_bad_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) decoder->pkt_len = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) decoder->pkt_step = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) intel_pt_decoder_log_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) } while (decoder->packet.type == INTEL_PT_PAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static uint64_t intel_pt_next_period(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) uint64_t timestamp, masked_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) timestamp = decoder->timestamp + decoder->timestamp_insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) masked_timestamp = timestamp & decoder->period_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (decoder->continuous_period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (masked_timestamp > decoder->last_masked_timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) timestamp += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) masked_timestamp = timestamp & decoder->period_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (masked_timestamp > decoder->last_masked_timestamp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) decoder->last_masked_timestamp = masked_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) decoder->continuous_period = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (masked_timestamp < decoder->last_masked_timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return decoder->period_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return decoder->period_ticks - (timestamp - masked_timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static uint64_t intel_pt_next_sample(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) switch (decoder->period_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) case INTEL_PT_PERIOD_INSTRUCTIONS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return decoder->period - decoder->period_insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) case INTEL_PT_PERIOD_TICKS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return intel_pt_next_period(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) case INTEL_PT_PERIOD_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) case INTEL_PT_PERIOD_MTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static void intel_pt_sample_insn(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) uint64_t timestamp, masked_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) switch (decoder->period_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) case INTEL_PT_PERIOD_INSTRUCTIONS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) decoder->period_insn_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) case INTEL_PT_PERIOD_TICKS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) timestamp = decoder->timestamp + decoder->timestamp_insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) masked_timestamp = timestamp & decoder->period_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (masked_timestamp > decoder->last_masked_timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) decoder->last_masked_timestamp = masked_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) decoder->last_masked_timestamp += decoder->period_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) case INTEL_PT_PERIOD_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) case INTEL_PT_PERIOD_MTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) decoder->state.type |= INTEL_PT_INSTRUCTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static int intel_pt_walk_insn(struct intel_pt_decoder *decoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct intel_pt_insn *intel_pt_insn, uint64_t ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) uint64_t max_insn_cnt, insn_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (!decoder->mtc_insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) decoder->mtc_insn = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) max_insn_cnt = intel_pt_next_sample(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) err = decoder->walk_insn(intel_pt_insn, &insn_cnt, &decoder->ip, ip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) max_insn_cnt, decoder->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) decoder->tot_insn_cnt += insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) decoder->timestamp_insn_cnt += insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) decoder->sample_insn_cnt += insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) decoder->period_insn_cnt += insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) decoder->no_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) decoder->pkt_state = INTEL_PT_STATE_ERR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) intel_pt_log_at("ERROR: Failed to get instruction",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) decoder->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (err == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return -ENOLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (ip && decoder->ip == ip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) err = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (max_insn_cnt && insn_cnt >= max_insn_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) intel_pt_sample_insn(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (intel_pt_insn->branch == INTEL_PT_BR_NO_BRANCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) decoder->state.type = INTEL_PT_INSTRUCTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) decoder->ip += intel_pt_insn->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) err = INTEL_PT_RETURN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (intel_pt_insn->op == INTEL_PT_OP_CALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* Zero-length calls are excluded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (intel_pt_insn->branch != INTEL_PT_BR_UNCONDITIONAL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) intel_pt_insn->rel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) err = intel_pt_push(&decoder->stack, decoder->ip +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) intel_pt_insn->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) } else if (intel_pt_insn->op == INTEL_PT_OP_RET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) decoder->ret_addr = intel_pt_pop(&decoder->stack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (intel_pt_insn->branch == INTEL_PT_BR_UNCONDITIONAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int cnt = decoder->no_progress++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) decoder->ip += intel_pt_insn->length +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) intel_pt_insn->rel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) decoder->state.to_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) err = INTEL_PT_RETURN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * Check for being stuck in a loop. This can happen if a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * decoder error results in the decoder erroneously setting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * ip to an address that is itself in an infinite loop that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * consumes no packets. When that happens, there must be an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * unconditional branch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (cnt == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) decoder->stuck_ip = decoder->state.to_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) decoder->stuck_ip_prd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) decoder->stuck_ip_cnt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) } else if (cnt > INTEL_PT_MAX_LOOPS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) decoder->state.to_ip == decoder->stuck_ip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) intel_pt_log_at("ERROR: Never-ending loop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) decoder->state.to_ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) decoder->pkt_state = INTEL_PT_STATE_ERR_RESYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) err = -ELOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) } else if (!--decoder->stuck_ip_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) decoder->stuck_ip_prd += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) decoder->stuck_ip_cnt = decoder->stuck_ip_prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) decoder->stuck_ip = decoder->state.to_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) goto out_no_progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) decoder->no_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) out_no_progress:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) decoder->state.insn_op = intel_pt_insn->op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) decoder->state.insn_len = intel_pt_insn->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) memcpy(decoder->state.insn, intel_pt_insn->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) INTEL_PT_INSN_BUF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (decoder->tx_flags & INTEL_PT_IN_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) decoder->state.flags |= INTEL_PT_IN_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static bool intel_pt_fup_event(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) enum intel_pt_sample_type type = decoder->state.type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) bool ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) decoder->state.type &= ~INTEL_PT_BRANCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (decoder->set_fup_tx_flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) decoder->set_fup_tx_flags = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) decoder->tx_flags = decoder->fup_tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) decoder->state.type |= INTEL_PT_TRANSACTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (decoder->fup_tx_flags & INTEL_PT_ABORT_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) decoder->state.type |= INTEL_PT_BRANCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) decoder->state.flags = decoder->fup_tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (decoder->set_fup_ptw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) decoder->set_fup_ptw = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) decoder->state.type |= INTEL_PT_PTW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) decoder->state.flags |= INTEL_PT_FUP_IP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) decoder->state.ptw_payload = decoder->fup_ptw_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (decoder->set_fup_mwait) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) decoder->set_fup_mwait = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) decoder->state.type |= INTEL_PT_MWAIT_OP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) decoder->state.mwait_payload = decoder->fup_mwait_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (decoder->set_fup_pwre) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) decoder->set_fup_pwre = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) decoder->state.type |= INTEL_PT_PWR_ENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) decoder->state.pwre_payload = decoder->fup_pwre_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (decoder->set_fup_exstop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) decoder->set_fup_exstop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) decoder->state.type |= INTEL_PT_EX_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) decoder->state.flags |= INTEL_PT_FUP_IP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (decoder->set_fup_bep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) decoder->set_fup_bep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) decoder->state.type |= INTEL_PT_BLK_ITEMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (decoder->overflow) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) decoder->overflow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (!ret && !decoder->pge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (decoder->hop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) decoder->state.type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) decoder->pkt_state = INTEL_PT_STATE_RESAMPLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) decoder->pge = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) decoder->state.type |= INTEL_PT_BRANCH | INTEL_PT_TRACE_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) decoder->state.from_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) decoder->state.to_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) decoder->state.type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static inline bool intel_pt_fup_with_nlip(struct intel_pt_decoder *decoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct intel_pt_insn *intel_pt_insn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) uint64_t ip, int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return decoder->flags & INTEL_PT_FUP_WITH_NLIP && !err &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) intel_pt_insn->branch == INTEL_PT_BR_INDIRECT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ip == decoder->ip + intel_pt_insn->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static int intel_pt_walk_fup(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct intel_pt_insn intel_pt_insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) uint64_t ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ip = decoder->last_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) err = intel_pt_walk_insn(decoder, &intel_pt_insn, ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (err == INTEL_PT_RETURN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (err == -EAGAIN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) intel_pt_fup_with_nlip(decoder, &intel_pt_insn, ip, err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) bool no_tip = decoder->pkt_state != INTEL_PT_STATE_FUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) decoder->pkt_state = INTEL_PT_STATE_IN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (intel_pt_fup_event(decoder) && no_tip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) decoder->set_fup_tx_flags = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (intel_pt_insn.branch == INTEL_PT_BR_INDIRECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) intel_pt_log_at("ERROR: Unexpected indirect branch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) decoder->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) decoder->pkt_state = INTEL_PT_STATE_ERR_RESYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (intel_pt_insn.branch == INTEL_PT_BR_CONDITIONAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) intel_pt_log_at("ERROR: Unexpected conditional branch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) decoder->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) decoder->pkt_state = INTEL_PT_STATE_ERR_RESYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) intel_pt_bug(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static int intel_pt_walk_tip(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct intel_pt_insn intel_pt_insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) err = intel_pt_walk_insn(decoder, &intel_pt_insn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (err == INTEL_PT_RETURN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) decoder->pgd_ip &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) decoder->pkt_state == INTEL_PT_STATE_TIP_PGD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) (decoder->state.type & INTEL_PT_BRANCH) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) decoder->pgd_ip(decoder->state.to_ip, decoder->data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* Unconditional branch leaving filter region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) decoder->no_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) decoder->pge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) decoder->continuous_period = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) decoder->pkt_state = INTEL_PT_STATE_IN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) decoder->state.type |= INTEL_PT_TRACE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (err == INTEL_PT_RETURN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (intel_pt_insn.branch == INTEL_PT_BR_INDIRECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (decoder->pkt_state == INTEL_PT_STATE_TIP_PGD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) decoder->pge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) decoder->continuous_period = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) decoder->pkt_state = INTEL_PT_STATE_IN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (decoder->packet.count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) decoder->state.to_ip = decoder->last_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) decoder->ip = decoder->last_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) decoder->state.type |= INTEL_PT_TRACE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) decoder->pkt_state = INTEL_PT_STATE_IN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (decoder->packet.count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) decoder->state.to_ip = decoder->last_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) decoder->ip = decoder->last_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (intel_pt_insn.branch == INTEL_PT_BR_CONDITIONAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) uint64_t to_ip = decoder->ip + intel_pt_insn.length +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) intel_pt_insn.rel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (decoder->pgd_ip &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) decoder->pkt_state == INTEL_PT_STATE_TIP_PGD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) decoder->pgd_ip(to_ip, decoder->data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* Conditional branch leaving filter region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) decoder->pge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) decoder->continuous_period = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) decoder->pkt_state = INTEL_PT_STATE_IN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) decoder->ip = to_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) decoder->state.to_ip = to_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) decoder->state.type |= INTEL_PT_TRACE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) intel_pt_log_at("ERROR: Conditional branch when expecting indirect branch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) decoder->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) decoder->pkt_state = INTEL_PT_STATE_ERR_RESYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return intel_pt_bug(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static int intel_pt_walk_tnt(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct intel_pt_insn intel_pt_insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) err = intel_pt_walk_insn(decoder, &intel_pt_insn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (err == INTEL_PT_RETURN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (intel_pt_insn.op == INTEL_PT_OP_RET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (!decoder->return_compression) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) intel_pt_log_at("ERROR: RET when expecting conditional branch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) decoder->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) decoder->pkt_state = INTEL_PT_STATE_ERR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (!decoder->ret_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) intel_pt_log_at("ERROR: Bad RET compression (stack empty)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) decoder->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) decoder->pkt_state = INTEL_PT_STATE_ERR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (!(decoder->tnt.payload & BIT63)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) intel_pt_log_at("ERROR: Bad RET compression (TNT=N)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) decoder->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) decoder->pkt_state = INTEL_PT_STATE_ERR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) decoder->tnt.count -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (decoder->tnt.count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) decoder->pkt_state = INTEL_PT_STATE_TNT_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) decoder->pkt_state = INTEL_PT_STATE_IN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) decoder->tnt.payload <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) decoder->ip = decoder->ret_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) decoder->state.to_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (intel_pt_insn.branch == INTEL_PT_BR_INDIRECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* Handle deferred TIPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) err = intel_pt_get_next_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (decoder->packet.type != INTEL_PT_TIP ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) decoder->packet.count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) intel_pt_log_at("ERROR: Missing deferred TIP for indirect branch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) decoder->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) decoder->pkt_state = INTEL_PT_STATE_ERR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) decoder->pkt_step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) intel_pt_set_last_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) decoder->state.to_ip = decoder->last_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) decoder->ip = decoder->last_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (intel_pt_insn.branch == INTEL_PT_BR_CONDITIONAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) decoder->tnt.count -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (decoder->tnt.count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) decoder->pkt_state = INTEL_PT_STATE_TNT_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) decoder->pkt_state = INTEL_PT_STATE_IN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (decoder->tnt.payload & BIT63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) decoder->tnt.payload <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) decoder->ip += intel_pt_insn.length +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) intel_pt_insn.rel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) decoder->state.to_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* Instruction sample for a non-taken branch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (decoder->state.type & INTEL_PT_INSTRUCTION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) decoder->tnt.payload <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) decoder->state.type = INTEL_PT_INSTRUCTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) decoder->ip += intel_pt_insn.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) decoder->sample_cyc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) decoder->ip += intel_pt_insn.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (!decoder->tnt.count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) intel_pt_update_sample_time(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) decoder->tnt.payload <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return intel_pt_bug(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) static int intel_pt_mode_tsx(struct intel_pt_decoder *decoder, bool *no_tip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) unsigned int fup_tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) fup_tx_flags = decoder->packet.payload &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) (INTEL_PT_IN_TX | INTEL_PT_ABORT_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) err = intel_pt_get_next_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (decoder->packet.type == INTEL_PT_FUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) decoder->fup_tx_flags = fup_tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) decoder->set_fup_tx_flags = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (!(decoder->fup_tx_flags & INTEL_PT_ABORT_TX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) *no_tip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) intel_pt_log_at("ERROR: Missing FUP after MODE.TSX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) decoder->pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) intel_pt_update_in_tx(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static uint64_t intel_pt_8b_tsc(uint64_t timestamp, uint64_t ref_timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) timestamp |= (ref_timestamp & (0xffULL << 56));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (timestamp < ref_timestamp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (ref_timestamp - timestamp > (1ULL << 55))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) timestamp += (1ULL << 56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (timestamp - ref_timestamp > (1ULL << 55))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) timestamp -= (1ULL << 56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static void intel_pt_calc_tsc_timestamp(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) uint64_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) decoder->have_tma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (decoder->ref_timestamp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) timestamp = intel_pt_8b_tsc(decoder->packet.payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) decoder->ref_timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) decoder->tsc_timestamp = timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) decoder->timestamp = timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) decoder->ref_timestamp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) decoder->timestamp_insn_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) } else if (decoder->timestamp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) timestamp = decoder->packet.payload |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) (decoder->timestamp & (0xffULL << 56));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) decoder->tsc_timestamp = timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (timestamp < decoder->timestamp &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) decoder->timestamp - timestamp < decoder->tsc_slip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) intel_pt_log_to("Suppressing backwards timestamp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) timestamp = decoder->timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (timestamp < decoder->timestamp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) intel_pt_log_to("Wraparound timestamp", timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) timestamp += (1ULL << 56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) decoder->tsc_timestamp = timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) decoder->timestamp = timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) decoder->timestamp_insn_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (decoder->last_packet_type == INTEL_PT_CYC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) decoder->cyc_ref_timestamp = decoder->timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) decoder->cycle_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) decoder->have_calc_cyc_to_tsc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) intel_pt_calc_cyc_to_tsc(decoder, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) intel_pt_log_to("Setting timestamp", decoder->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static int intel_pt_overflow(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) intel_pt_log("ERROR: Buffer overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) intel_pt_clear_tx_flags(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) decoder->timestamp_insn_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) decoder->pkt_state = INTEL_PT_STATE_IN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) decoder->ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) decoder->pge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) decoder->set_fup_tx_flags = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) decoder->set_fup_ptw = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) decoder->set_fup_mwait = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) decoder->set_fup_pwre = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) decoder->set_fup_exstop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) decoder->set_fup_bep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) decoder->overflow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) return -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static inline void intel_pt_mtc_cyc_cnt_pge(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (decoder->have_cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) decoder->cyc_cnt_timestamp = decoder->timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) decoder->base_cyc_cnt = decoder->tot_cyc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static inline void intel_pt_mtc_cyc_cnt_cbr(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) decoder->tsc_to_cyc = decoder->cbr / decoder->max_non_turbo_ratio_fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (decoder->pge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) intel_pt_mtc_cyc_cnt_pge(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static inline void intel_pt_mtc_cyc_cnt_upd(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) uint64_t tot_cyc_cnt, tsc_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (decoder->have_cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) decoder->sample_cyc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (!decoder->pge || decoder->timestamp <= decoder->cyc_cnt_timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) tsc_delta = decoder->timestamp - decoder->cyc_cnt_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) tot_cyc_cnt = tsc_delta * decoder->tsc_to_cyc + decoder->base_cyc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) if (tot_cyc_cnt > decoder->tot_cyc_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) decoder->tot_cyc_cnt = tot_cyc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) static void intel_pt_calc_tma(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) uint32_t ctc = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) uint32_t fc = decoder->packet.count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) uint32_t ctc_rem = ctc & decoder->ctc_rem_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (!decoder->tsc_ctc_ratio_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (decoder->pge && !decoder->in_psb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) intel_pt_mtc_cyc_cnt_pge(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) intel_pt_mtc_cyc_cnt_upd(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) decoder->last_mtc = (ctc >> decoder->mtc_shift) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) decoder->ctc_timestamp = decoder->tsc_timestamp - fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (decoder->tsc_ctc_mult) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) decoder->ctc_timestamp -= ctc_rem * decoder->tsc_ctc_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) decoder->ctc_timestamp -= multdiv(ctc_rem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) decoder->tsc_ctc_ratio_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) decoder->tsc_ctc_ratio_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) decoder->ctc_delta = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) decoder->have_tma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) decoder->fixup_last_mtc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) intel_pt_log("CTC timestamp " x64_fmt " last MTC %#x CTC rem %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) decoder->ctc_timestamp, decoder->last_mtc, ctc_rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static void intel_pt_calc_mtc_timestamp(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) uint64_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) uint32_t mtc, mtc_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (!decoder->have_tma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) mtc = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (decoder->mtc_shift > 8 && decoder->fixup_last_mtc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) decoder->fixup_last_mtc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) intel_pt_fixup_last_mtc(mtc, decoder->mtc_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) &decoder->last_mtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (mtc > decoder->last_mtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) mtc_delta = mtc - decoder->last_mtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) mtc_delta = mtc + 256 - decoder->last_mtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) decoder->ctc_delta += mtc_delta << decoder->mtc_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (decoder->tsc_ctc_mult) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) timestamp = decoder->ctc_timestamp +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) decoder->ctc_delta * decoder->tsc_ctc_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) timestamp = decoder->ctc_timestamp +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) multdiv(decoder->ctc_delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) decoder->tsc_ctc_ratio_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) decoder->tsc_ctc_ratio_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (timestamp < decoder->timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) intel_pt_log("Suppressing MTC timestamp " x64_fmt " less than current timestamp " x64_fmt "\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) timestamp, decoder->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) decoder->timestamp = timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) intel_pt_mtc_cyc_cnt_upd(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) decoder->timestamp_insn_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) decoder->last_mtc = mtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (decoder->last_packet_type == INTEL_PT_CYC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) decoder->cyc_ref_timestamp = decoder->timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) decoder->cycle_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) decoder->have_calc_cyc_to_tsc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) intel_pt_calc_cyc_to_tsc(decoder, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) intel_pt_log_to("Setting timestamp", decoder->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) static void intel_pt_calc_cbr(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) unsigned int cbr = decoder->packet.payload & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) decoder->cbr_payload = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (decoder->cbr == cbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) decoder->cbr = cbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) decoder->cbr_cyc_to_tsc = decoder->max_non_turbo_ratio_fp / cbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) intel_pt_mtc_cyc_cnt_cbr(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) static void intel_pt_calc_cyc_timestamp(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) uint64_t timestamp = decoder->cyc_ref_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) decoder->have_cyc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) decoder->cycle_cnt += decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (decoder->pge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) decoder->tot_cyc_cnt += decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) decoder->sample_cyc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (!decoder->cyc_ref_timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (decoder->have_calc_cyc_to_tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) timestamp += decoder->cycle_cnt * decoder->calc_cyc_to_tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) else if (decoder->cbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) timestamp += decoder->cycle_cnt * decoder->cbr_cyc_to_tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (timestamp < decoder->timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) intel_pt_log("Suppressing CYC timestamp " x64_fmt " less than current timestamp " x64_fmt "\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) timestamp, decoder->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) decoder->timestamp = timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) decoder->timestamp_insn_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) intel_pt_log_to("Setting timestamp", decoder->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static void intel_pt_bbp(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (decoder->prev_pkt_ctx == INTEL_PT_NO_CTX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) memset(decoder->state.items.mask, 0, sizeof(decoder->state.items.mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) decoder->state.items.is_32_bit = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) decoder->blk_type = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) decoder->blk_type_pos = intel_pt_blk_type_pos(decoder->blk_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (decoder->blk_type == INTEL_PT_GP_REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) decoder->state.items.is_32_bit = decoder->packet.count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) if (decoder->blk_type_pos < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) intel_pt_log("WARNING: Unknown block type %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) decoder->blk_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) } else if (decoder->state.items.mask[decoder->blk_type_pos]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) intel_pt_log("WARNING: Duplicate block type %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) decoder->blk_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) static void intel_pt_bip(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) uint32_t id = decoder->packet.count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) uint32_t bit = 1 << id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) int pos = decoder->blk_type_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (pos < 0 || id >= INTEL_PT_BLK_ITEM_ID_CNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) intel_pt_log("WARNING: Unknown block item %u type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) id, decoder->blk_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (decoder->state.items.mask[pos] & bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) intel_pt_log("WARNING: Duplicate block item %u type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) id, decoder->blk_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) decoder->state.items.mask[pos] |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) decoder->state.items.val[pos][id] = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /* Walk PSB+ packets when already in sync. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) static int intel_pt_walk_psbend(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) decoder->in_psb = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) err = intel_pt_get_next_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) switch (decoder->packet.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) case INTEL_PT_PSBEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) case INTEL_PT_TIP_PGD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) case INTEL_PT_TIP_PGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) case INTEL_PT_TIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) case INTEL_PT_TNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) case INTEL_PT_TRACESTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) case INTEL_PT_BAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) case INTEL_PT_PSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) case INTEL_PT_PTWRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) case INTEL_PT_PTWRITE_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) case INTEL_PT_EXSTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) case INTEL_PT_EXSTOP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) case INTEL_PT_MWAIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) case INTEL_PT_PWRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) case INTEL_PT_PWRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) case INTEL_PT_BBP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) case INTEL_PT_BIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) case INTEL_PT_BEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) case INTEL_PT_BEP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) decoder->have_tma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) intel_pt_log("ERROR: Unexpected packet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) err = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) case INTEL_PT_OVF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) err = intel_pt_overflow(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) case INTEL_PT_TSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) intel_pt_calc_tsc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) case INTEL_PT_TMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) intel_pt_calc_tma(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) case INTEL_PT_CBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) intel_pt_calc_cbr(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) case INTEL_PT_MODE_EXEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) decoder->exec_mode = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) case INTEL_PT_PIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) decoder->cr3 = decoder->packet.payload & (BIT63 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) case INTEL_PT_FUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) decoder->pge = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (decoder->packet.count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) intel_pt_set_last_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (decoder->hop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) /* Act on FUP at PSBEND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) decoder->ip = decoder->last_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) decoder->hop_psb_fup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) case INTEL_PT_MODE_TSX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) intel_pt_update_in_tx(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) case INTEL_PT_MTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) intel_pt_calc_mtc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (decoder->period_type == INTEL_PT_PERIOD_MTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) decoder->state.type |= INTEL_PT_INSTRUCTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) case INTEL_PT_CYC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) intel_pt_calc_cyc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) case INTEL_PT_VMCS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) case INTEL_PT_MNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) case INTEL_PT_PAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) decoder->in_psb = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) static int intel_pt_walk_fup_tip(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (decoder->tx_flags & INTEL_PT_ABORT_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) decoder->tx_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) decoder->state.flags &= ~INTEL_PT_IN_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) decoder->state.flags |= INTEL_PT_ABORT_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) decoder->state.flags |= INTEL_PT_ASYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) err = intel_pt_get_next_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) switch (decoder->packet.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) case INTEL_PT_TNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) case INTEL_PT_FUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) case INTEL_PT_TRACESTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) case INTEL_PT_PSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) case INTEL_PT_TSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) case INTEL_PT_TMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) case INTEL_PT_MODE_TSX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) case INTEL_PT_BAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) case INTEL_PT_PSBEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) case INTEL_PT_PTWRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) case INTEL_PT_PTWRITE_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) case INTEL_PT_EXSTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) case INTEL_PT_EXSTOP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) case INTEL_PT_MWAIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) case INTEL_PT_PWRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) case INTEL_PT_PWRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) case INTEL_PT_BBP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) case INTEL_PT_BIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) case INTEL_PT_BEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) case INTEL_PT_BEP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) intel_pt_log("ERROR: Missing TIP after FUP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) decoder->pkt_state = INTEL_PT_STATE_ERR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) decoder->pkt_step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) case INTEL_PT_CBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) intel_pt_calc_cbr(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) case INTEL_PT_OVF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) return intel_pt_overflow(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) case INTEL_PT_TIP_PGD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) if (decoder->packet.count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) intel_pt_set_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) decoder->state.to_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) decoder->pge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) decoder->continuous_period = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) decoder->state.type |= INTEL_PT_TRACE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) case INTEL_PT_TIP_PGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) decoder->pge = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) intel_pt_log("Omitting PGE ip " x64_fmt "\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) decoder->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) decoder->state.from_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (decoder->packet.count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) intel_pt_set_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) decoder->state.to_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) decoder->state.type |= INTEL_PT_TRACE_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) intel_pt_mtc_cyc_cnt_pge(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) case INTEL_PT_TIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) if (decoder->packet.count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) intel_pt_set_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) decoder->state.to_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) case INTEL_PT_PIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) decoder->cr3 = decoder->packet.payload & (BIT63 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) case INTEL_PT_MTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) intel_pt_calc_mtc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (decoder->period_type == INTEL_PT_PERIOD_MTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) decoder->state.type |= INTEL_PT_INSTRUCTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) case INTEL_PT_CYC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) intel_pt_calc_cyc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) case INTEL_PT_MODE_EXEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) decoder->exec_mode = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) case INTEL_PT_VMCS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) case INTEL_PT_MNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) case INTEL_PT_PAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) return intel_pt_bug(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static int intel_pt_resample(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) decoder->pkt_state = INTEL_PT_STATE_IN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) decoder->state.type = INTEL_PT_INSTRUCTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #define HOP_PROCESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define HOP_IGNORE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define HOP_RETURN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) #define HOP_AGAIN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) static int intel_pt_scan_for_psb(struct intel_pt_decoder *decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) /* Hop mode: Ignore TNT, do not walk code, but get ip from FUPs and TIPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) static int intel_pt_hop_trace(struct intel_pt_decoder *decoder, bool *no_tip, int *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) *err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) /* Leap from PSB to PSB, getting ip from FUP within PSB+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (decoder->leap && !decoder->in_psb && decoder->packet.type != INTEL_PT_PSB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) *err = intel_pt_scan_for_psb(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (*err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return HOP_RETURN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) switch (decoder->packet.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) case INTEL_PT_TNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) return HOP_IGNORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) case INTEL_PT_TIP_PGD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) decoder->pge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (!decoder->packet.count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) return HOP_IGNORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) intel_pt_set_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) decoder->state.type |= INTEL_PT_TRACE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) decoder->state.from_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) decoder->state.to_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) return HOP_RETURN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) case INTEL_PT_TIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) if (!decoder->packet.count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) return HOP_IGNORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) intel_pt_set_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) decoder->state.type = INTEL_PT_INSTRUCTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) return HOP_RETURN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) case INTEL_PT_FUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) if (!decoder->packet.count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) return HOP_IGNORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) intel_pt_set_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) if (decoder->set_fup_mwait || decoder->set_fup_pwre)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) *no_tip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (!decoder->branch_enable || !decoder->pge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) *no_tip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) if (*no_tip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) decoder->state.type = INTEL_PT_INSTRUCTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) intel_pt_fup_event(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) return HOP_RETURN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) intel_pt_fup_event(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) decoder->state.type |= INTEL_PT_INSTRUCTION | INTEL_PT_BRANCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) *err = intel_pt_walk_fup_tip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (!*err && decoder->state.to_ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) decoder->pkt_state = INTEL_PT_STATE_RESAMPLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) return HOP_RETURN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) case INTEL_PT_PSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) decoder->last_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) decoder->have_last_ip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) decoder->hop_psb_fup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) *err = intel_pt_walk_psbend(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) if (*err == -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) return HOP_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (*err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) return HOP_RETURN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) if (decoder->hop_psb_fup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) decoder->hop_psb_fup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) decoder->state.type = INTEL_PT_INSTRUCTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) return HOP_RETURN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) if (decoder->cbr != decoder->cbr_seen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) decoder->state.type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) return HOP_RETURN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) return HOP_IGNORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) case INTEL_PT_BAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) case INTEL_PT_PAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) case INTEL_PT_TIP_PGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) case INTEL_PT_TSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) case INTEL_PT_TMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) case INTEL_PT_MODE_EXEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) case INTEL_PT_MODE_TSX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) case INTEL_PT_MTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) case INTEL_PT_CYC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) case INTEL_PT_VMCS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) case INTEL_PT_PSBEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) case INTEL_PT_CBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) case INTEL_PT_TRACESTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) case INTEL_PT_PIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) case INTEL_PT_OVF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) case INTEL_PT_MNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) case INTEL_PT_PTWRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) case INTEL_PT_PTWRITE_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) case INTEL_PT_EXSTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) case INTEL_PT_EXSTOP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) case INTEL_PT_MWAIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) case INTEL_PT_PWRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) case INTEL_PT_PWRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) case INTEL_PT_BBP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) case INTEL_PT_BIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) case INTEL_PT_BEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) case INTEL_PT_BEP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) return HOP_PROCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) static int intel_pt_walk_trace(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) int last_packet_type = INTEL_PT_PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) bool no_tip = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) err = intel_pt_get_next_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) if (decoder->cyc_threshold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if (decoder->sample_cyc && last_packet_type != INTEL_PT_CYC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) decoder->sample_cyc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) last_packet_type = decoder->packet.type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) if (decoder->hop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) switch (intel_pt_hop_trace(decoder, &no_tip, &err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) case HOP_IGNORE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) case HOP_RETURN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) case HOP_AGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) switch (decoder->packet.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) case INTEL_PT_TNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) if (!decoder->packet.count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) decoder->tnt = decoder->packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) decoder->pkt_state = INTEL_PT_STATE_TNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) err = intel_pt_walk_tnt(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) if (err == -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) case INTEL_PT_TIP_PGD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) if (decoder->packet.count != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) intel_pt_set_last_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) decoder->pkt_state = INTEL_PT_STATE_TIP_PGD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) return intel_pt_walk_tip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) case INTEL_PT_TIP_PGE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) decoder->pge = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) decoder->overflow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) intel_pt_mtc_cyc_cnt_pge(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) if (decoder->packet.count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) intel_pt_log_at("Skipping zero TIP.PGE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) decoder->pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) intel_pt_set_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) decoder->state.from_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) decoder->state.to_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) decoder->state.type |= INTEL_PT_TRACE_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) * In hop mode, resample to get the to_ip as an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) * "instruction" sample.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) if (decoder->hop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) decoder->pkt_state = INTEL_PT_STATE_RESAMPLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) case INTEL_PT_OVF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) return intel_pt_overflow(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) case INTEL_PT_TIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if (decoder->packet.count != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) intel_pt_set_last_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) decoder->pkt_state = INTEL_PT_STATE_TIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) return intel_pt_walk_tip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) case INTEL_PT_FUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if (decoder->packet.count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) intel_pt_log_at("Skipping zero FUP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) decoder->pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) no_tip = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) intel_pt_set_last_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) if (!decoder->branch_enable || !decoder->pge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) decoder->ip = decoder->last_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (intel_pt_fup_event(decoder))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) no_tip = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if (decoder->set_fup_mwait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) no_tip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (no_tip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) decoder->pkt_state = INTEL_PT_STATE_FUP_NO_TIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) decoder->pkt_state = INTEL_PT_STATE_FUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) err = intel_pt_walk_fup(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (err != -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) if (no_tip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) no_tip = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) return intel_pt_walk_fup_tip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) case INTEL_PT_TRACESTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) decoder->pge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) decoder->continuous_period = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) intel_pt_clear_tx_flags(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) decoder->have_tma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) case INTEL_PT_PSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) decoder->last_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) decoder->have_last_ip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) intel_pt_clear_stack(&decoder->stack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) err = intel_pt_walk_psbend(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (err == -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) * PSB+ CBR will not have changed but cater for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) * possibility of another CBR change that gets caught up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) * in the PSB+.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) if (decoder->cbr != decoder->cbr_seen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) decoder->state.type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) case INTEL_PT_PIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) decoder->cr3 = decoder->packet.payload & (BIT63 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) case INTEL_PT_MTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) intel_pt_calc_mtc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) if (decoder->period_type != INTEL_PT_PERIOD_MTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) * Ensure that there has been an instruction since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) * last MTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) if (!decoder->mtc_insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) decoder->mtc_insn = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) /* Ensure that there is a timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) if (!decoder->timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) decoder->state.type = INTEL_PT_INSTRUCTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) decoder->mtc_insn = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) case INTEL_PT_TSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) intel_pt_calc_tsc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) case INTEL_PT_TMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) intel_pt_calc_tma(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) case INTEL_PT_CYC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) intel_pt_calc_cyc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) case INTEL_PT_CBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) intel_pt_calc_cbr(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) if (decoder->cbr != decoder->cbr_seen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) decoder->state.type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) case INTEL_PT_MODE_EXEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) decoder->exec_mode = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) case INTEL_PT_MODE_TSX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) /* MODE_TSX need not be followed by FUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) if (!decoder->pge || decoder->in_psb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) intel_pt_update_in_tx(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) err = intel_pt_mode_tsx(decoder, &no_tip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) case INTEL_PT_BAD: /* Does not happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) return intel_pt_bug(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) case INTEL_PT_PSBEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) case INTEL_PT_VMCS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) case INTEL_PT_MNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) case INTEL_PT_PAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) case INTEL_PT_PTWRITE_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) decoder->fup_ptw_payload = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) err = intel_pt_get_next_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) if (decoder->packet.type == INTEL_PT_FUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) decoder->set_fup_ptw = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) no_tip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) intel_pt_log_at("ERROR: Missing FUP after PTWRITE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) decoder->pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) case INTEL_PT_PTWRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) decoder->state.type = INTEL_PT_PTW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) decoder->state.ptw_payload = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) case INTEL_PT_MWAIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) decoder->fup_mwait_payload = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) decoder->set_fup_mwait = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) case INTEL_PT_PWRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) if (decoder->set_fup_mwait) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) decoder->fup_pwre_payload =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) decoder->set_fup_pwre = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) decoder->state.type = INTEL_PT_PWR_ENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) decoder->state.pwrx_payload = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) case INTEL_PT_EXSTOP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) err = intel_pt_get_next_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) if (decoder->packet.type == INTEL_PT_FUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) decoder->set_fup_exstop = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) no_tip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) intel_pt_log_at("ERROR: Missing FUP after EXSTOP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) decoder->pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) case INTEL_PT_EXSTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) decoder->state.type = INTEL_PT_EX_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) case INTEL_PT_PWRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) decoder->state.type = INTEL_PT_PWR_EXIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) decoder->state.pwrx_payload = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) case INTEL_PT_BBP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) intel_pt_bbp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) case INTEL_PT_BIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) intel_pt_bip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) case INTEL_PT_BEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) decoder->state.type = INTEL_PT_BLK_ITEMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) case INTEL_PT_BEP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) err = intel_pt_get_next_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) if (decoder->packet.type == INTEL_PT_FUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) decoder->set_fup_bep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) no_tip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) intel_pt_log_at("ERROR: Missing FUP after BEP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) decoder->pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) return intel_pt_bug(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) static inline bool intel_pt_have_ip(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) return decoder->packet.count &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) (decoder->have_last_ip || decoder->packet.count == 3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) decoder->packet.count == 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) /* Walk PSB+ packets to get in sync. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) static int intel_pt_walk_psb(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) decoder->in_psb = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) err = intel_pt_get_next_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) switch (decoder->packet.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) case INTEL_PT_TIP_PGD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) decoder->continuous_period = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) __fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) case INTEL_PT_TIP_PGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) case INTEL_PT_TIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) case INTEL_PT_PTWRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) case INTEL_PT_PTWRITE_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) case INTEL_PT_EXSTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) case INTEL_PT_EXSTOP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) case INTEL_PT_MWAIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) case INTEL_PT_PWRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) case INTEL_PT_PWRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) case INTEL_PT_BBP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) case INTEL_PT_BIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) case INTEL_PT_BEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) case INTEL_PT_BEP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) intel_pt_log("ERROR: Unexpected packet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) err = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) case INTEL_PT_FUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) decoder->pge = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) if (intel_pt_have_ip(decoder)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) uint64_t current_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) intel_pt_set_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) if (current_ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) intel_pt_log_to("Setting IP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) decoder->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) case INTEL_PT_MTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) intel_pt_calc_mtc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) case INTEL_PT_TSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) intel_pt_calc_tsc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) case INTEL_PT_TMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) intel_pt_calc_tma(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) case INTEL_PT_CYC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) intel_pt_calc_cyc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) case INTEL_PT_CBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) intel_pt_calc_cbr(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) case INTEL_PT_PIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) decoder->cr3 = decoder->packet.payload & (BIT63 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) case INTEL_PT_MODE_EXEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) decoder->exec_mode = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) case INTEL_PT_MODE_TSX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) intel_pt_update_in_tx(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) case INTEL_PT_TRACESTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) decoder->pge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) decoder->continuous_period = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) intel_pt_clear_tx_flags(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) __fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) case INTEL_PT_TNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) decoder->have_tma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) intel_pt_log("ERROR: Unexpected packet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) if (decoder->ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) decoder->pkt_state = INTEL_PT_STATE_ERR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) decoder->pkt_state = INTEL_PT_STATE_ERR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) err = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) case INTEL_PT_BAD: /* Does not happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) err = intel_pt_bug(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) case INTEL_PT_OVF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) err = intel_pt_overflow(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) case INTEL_PT_PSBEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) case INTEL_PT_PSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) case INTEL_PT_VMCS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) case INTEL_PT_MNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) case INTEL_PT_PAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) decoder->in_psb = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) static int intel_pt_walk_to_ip(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) err = intel_pt_get_next_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) switch (decoder->packet.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) case INTEL_PT_TIP_PGD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) decoder->continuous_period = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) decoder->pge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) if (intel_pt_have_ip(decoder))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) intel_pt_set_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) if (!decoder->ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) decoder->state.type |= INTEL_PT_TRACE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) case INTEL_PT_TIP_PGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) decoder->pge = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) intel_pt_mtc_cyc_cnt_pge(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) if (intel_pt_have_ip(decoder))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) intel_pt_set_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) if (!decoder->ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) decoder->state.type |= INTEL_PT_TRACE_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) case INTEL_PT_TIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) decoder->pge = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) if (intel_pt_have_ip(decoder))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) intel_pt_set_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) if (!decoder->ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) case INTEL_PT_FUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) if (intel_pt_have_ip(decoder))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) intel_pt_set_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) if (decoder->ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) case INTEL_PT_MTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) intel_pt_calc_mtc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) case INTEL_PT_TSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) intel_pt_calc_tsc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) case INTEL_PT_TMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) intel_pt_calc_tma(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) case INTEL_PT_CYC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) intel_pt_calc_cyc_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) case INTEL_PT_CBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) intel_pt_calc_cbr(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) case INTEL_PT_PIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) decoder->cr3 = decoder->packet.payload & (BIT63 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) case INTEL_PT_MODE_EXEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) decoder->exec_mode = decoder->packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) case INTEL_PT_MODE_TSX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) intel_pt_update_in_tx(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) case INTEL_PT_OVF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) return intel_pt_overflow(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) case INTEL_PT_BAD: /* Does not happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) return intel_pt_bug(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) case INTEL_PT_TRACESTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) decoder->pge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) decoder->continuous_period = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) intel_pt_clear_tx_flags(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) decoder->have_tma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) case INTEL_PT_PSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) decoder->last_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) decoder->have_last_ip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) intel_pt_clear_stack(&decoder->stack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) err = intel_pt_walk_psb(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) if (decoder->ip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) /* Do not have a sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) decoder->state.type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) case INTEL_PT_TNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) case INTEL_PT_PSBEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) case INTEL_PT_VMCS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) case INTEL_PT_MNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) case INTEL_PT_PAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) case INTEL_PT_PTWRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) case INTEL_PT_PTWRITE_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) case INTEL_PT_EXSTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) case INTEL_PT_EXSTOP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) case INTEL_PT_MWAIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) case INTEL_PT_PWRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) case INTEL_PT_PWRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) case INTEL_PT_BBP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) case INTEL_PT_BIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) case INTEL_PT_BEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) case INTEL_PT_BEP_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) static int intel_pt_sync_ip(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) decoder->set_fup_tx_flags = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) decoder->set_fup_ptw = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) decoder->set_fup_mwait = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) decoder->set_fup_pwre = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) decoder->set_fup_exstop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) decoder->set_fup_bep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) decoder->overflow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) if (!decoder->branch_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) decoder->pkt_state = INTEL_PT_STATE_IN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) decoder->state.type = 0; /* Do not have a sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) intel_pt_log("Scanning for full IP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) err = intel_pt_walk_to_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) /* In hop mode, resample to get the to_ip as an "instruction" sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) if (decoder->hop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) decoder->pkt_state = INTEL_PT_STATE_RESAMPLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) decoder->pkt_state = INTEL_PT_STATE_IN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) decoder->state.from_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) decoder->state.to_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) intel_pt_log_to("Setting IP", decoder->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) static int intel_pt_part_psb(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) const unsigned char *end = decoder->buf + decoder->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) for (i = INTEL_PT_PSB_LEN - 1; i; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) if (i > decoder->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) if (!memcmp(end - i, INTEL_PT_PSB_STR, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) static int intel_pt_rest_psb(struct intel_pt_decoder *decoder, int part_psb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) size_t rest_psb = INTEL_PT_PSB_LEN - part_psb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) const char *psb = INTEL_PT_PSB_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) if (rest_psb > decoder->len ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) memcmp(decoder->buf, psb + part_psb, rest_psb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) return rest_psb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) static int intel_pt_get_split_psb(struct intel_pt_decoder *decoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) int part_psb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) int rest_psb, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) decoder->pos += decoder->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) decoder->len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) ret = intel_pt_get_next_data(decoder, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) rest_psb = intel_pt_rest_psb(decoder, part_psb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) if (!rest_psb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) decoder->pos -= part_psb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) decoder->next_buf = decoder->buf + rest_psb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) decoder->next_len = decoder->len - rest_psb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) memcpy(decoder->temp_buf, INTEL_PT_PSB_STR, INTEL_PT_PSB_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) decoder->buf = decoder->temp_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) decoder->len = INTEL_PT_PSB_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) static int intel_pt_scan_for_psb(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) unsigned char *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) intel_pt_log("Scanning for PSB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) if (!decoder->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) ret = intel_pt_get_next_data(decoder, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) next = memmem(decoder->buf, decoder->len, INTEL_PT_PSB_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) INTEL_PT_PSB_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) if (!next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) int part_psb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) part_psb = intel_pt_part_psb(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) if (part_psb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) ret = intel_pt_get_split_psb(decoder, part_psb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) decoder->pos += decoder->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) decoder->len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) decoder->pkt_step = next - decoder->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) return intel_pt_get_next_packet(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) static int intel_pt_sync(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) decoder->pge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) decoder->continuous_period = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) decoder->have_last_ip = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) decoder->last_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) decoder->ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) intel_pt_clear_stack(&decoder->stack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) leap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) err = intel_pt_scan_for_psb(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) decoder->have_last_ip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) decoder->pkt_state = INTEL_PT_STATE_IN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) err = intel_pt_walk_psb(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) if (decoder->ip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) decoder->state.type = 0; /* Do not have a sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) * In hop mode, resample to get the PSB FUP ip as an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) * "instruction" sample.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) if (decoder->hop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) decoder->pkt_state = INTEL_PT_STATE_RESAMPLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) decoder->pkt_state = INTEL_PT_STATE_IN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) } else if (decoder->leap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) * In leap mode, only PSB+ is decoded, so keeping leaping to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) * next PSB until there is an ip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) goto leap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) return intel_pt_sync_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) static uint64_t intel_pt_est_timestamp(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) uint64_t est = decoder->sample_insn_cnt << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) if (!decoder->cbr || !decoder->max_non_turbo_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) est *= decoder->max_non_turbo_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) est /= decoder->cbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) return decoder->sample_timestamp + est;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) const struct intel_pt_state *intel_pt_decode(struct intel_pt_decoder *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) decoder->state.type = INTEL_PT_BRANCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) decoder->state.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) switch (decoder->pkt_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) case INTEL_PT_STATE_NO_PSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) err = intel_pt_sync(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) case INTEL_PT_STATE_NO_IP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) decoder->have_last_ip = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) decoder->last_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) decoder->ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) __fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) case INTEL_PT_STATE_ERR_RESYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) err = intel_pt_sync_ip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) case INTEL_PT_STATE_IN_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) err = intel_pt_walk_trace(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) case INTEL_PT_STATE_TNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) case INTEL_PT_STATE_TNT_CONT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) err = intel_pt_walk_tnt(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) if (err == -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) err = intel_pt_walk_trace(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) case INTEL_PT_STATE_TIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) case INTEL_PT_STATE_TIP_PGD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) err = intel_pt_walk_tip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) case INTEL_PT_STATE_FUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) err = intel_pt_walk_fup(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) if (err == -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) err = intel_pt_walk_fup_tip(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) case INTEL_PT_STATE_FUP_NO_TIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) err = intel_pt_walk_fup(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) if (err == -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) err = intel_pt_walk_trace(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) case INTEL_PT_STATE_RESAMPLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) err = intel_pt_resample(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) err = intel_pt_bug(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) } while (err == -ENOLINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) decoder->state.err = intel_pt_ext_err(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) if (err != -EOVERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) intel_pt_update_sample_time(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) decoder->sample_tot_cyc_cnt = decoder->tot_cyc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) decoder->state.err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) if (decoder->cbr != decoder->cbr_seen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) decoder->cbr_seen = decoder->cbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) if (!decoder->state.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) decoder->state.from_ip = decoder->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) decoder->state.to_ip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) decoder->state.type |= INTEL_PT_CBR_CHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) decoder->state.cbr_payload = decoder->cbr_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) decoder->state.cbr = decoder->cbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) if (intel_pt_sample_time(decoder->pkt_state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) intel_pt_update_sample_time(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) if (decoder->sample_cyc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) decoder->sample_tot_cyc_cnt = decoder->tot_cyc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) decoder->state.flags |= INTEL_PT_SAMPLE_IPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) decoder->sample_cyc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) * When using only TSC/MTC to compute cycles, IPC can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) * sampled as soon as the cycle count changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) if (!decoder->have_cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) decoder->state.flags |= INTEL_PT_SAMPLE_IPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) decoder->state.timestamp = decoder->sample_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) decoder->state.est_timestamp = intel_pt_est_timestamp(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) decoder->state.cr3 = decoder->cr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) decoder->state.tot_insn_cnt = decoder->tot_insn_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) decoder->state.tot_cyc_cnt = decoder->sample_tot_cyc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) return &decoder->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) * intel_pt_next_psb - move buffer pointer to the start of the next PSB packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) * @buf: pointer to buffer pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) * @len: size of buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) * Updates the buffer pointer to point to the start of the next PSB packet if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) * there is one, otherwise the buffer pointer is unchanged. If @buf is updated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) * @len is adjusted accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) * Return: %true if a PSB packet is found, %false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) static bool intel_pt_next_psb(unsigned char **buf, size_t *len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) unsigned char *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) next = memmem(*buf, *len, INTEL_PT_PSB_STR, INTEL_PT_PSB_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) if (next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) *len -= next - *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) *buf = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) * intel_pt_step_psb - move buffer pointer to the start of the following PSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) * packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) * @buf: pointer to buffer pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) * @len: size of buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) * Updates the buffer pointer to point to the start of the following PSB packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) * (skipping the PSB at @buf itself) if there is one, otherwise the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) * pointer is unchanged. If @buf is updated, @len is adjusted accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) * Return: %true if a PSB packet is found, %false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) static bool intel_pt_step_psb(unsigned char **buf, size_t *len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) unsigned char *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) if (!*len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) next = memmem(*buf + 1, *len - 1, INTEL_PT_PSB_STR, INTEL_PT_PSB_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) if (next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) *len -= next - *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) *buf = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) * intel_pt_last_psb - find the last PSB packet in a buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) * @buf: buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) * @len: size of buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) * This function finds the last PSB in a buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) * Return: A pointer to the last PSB in @buf if found, %NULL otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) static unsigned char *intel_pt_last_psb(unsigned char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) const char *n = INTEL_PT_PSB_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) unsigned char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) size_t k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) if (len < INTEL_PT_PSB_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) k = len - INTEL_PT_PSB_LEN + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) p = memrchr(buf, n[0], k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) if (!memcmp(p + 1, n + 1, INTEL_PT_PSB_LEN - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) return p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) k = p - buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) if (!k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) * intel_pt_next_tsc - find and return next TSC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) * @buf: buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) * @len: size of buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) * @tsc: TSC value returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) * @rem: returns remaining size when TSC is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) * Find a TSC packet in @buf and return the TSC value. This function assumes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) * that @buf starts at a PSB and that PSB+ will contain TSC and so stops if a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) * PSBEND packet is found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) * Return: %true if TSC is found, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) static bool intel_pt_next_tsc(unsigned char *buf, size_t len, uint64_t *tsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) size_t *rem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) enum intel_pt_pkt_ctx ctx = INTEL_PT_NO_CTX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) struct intel_pt_pkt packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) ret = intel_pt_get_packet(buf, len, &packet, &ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) if (packet.type == INTEL_PT_TSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) *tsc = packet.payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) *rem = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) if (packet.type == INTEL_PT_PSBEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) buf += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) len -= ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) * intel_pt_tsc_cmp - compare 7-byte TSCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) * @tsc1: first TSC to compare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) * @tsc2: second TSC to compare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) * This function compares 7-byte TSC values allowing for the possibility that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) * TSC wrapped around. Generally it is not possible to know if TSC has wrapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) * around so for that purpose this function assumes the absolute difference is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) * less than half the maximum difference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) * Return: %-1 if @tsc1 is before @tsc2, %0 if @tsc1 == @tsc2, %1 if @tsc1 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) * after @tsc2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) static int intel_pt_tsc_cmp(uint64_t tsc1, uint64_t tsc2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) const uint64_t halfway = (1ULL << 55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) if (tsc1 == tsc2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) if (tsc1 < tsc2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) if (tsc2 - tsc1 < halfway)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) if (tsc1 - tsc2 < halfway)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) #define MAX_PADDING (PERF_AUXTRACE_RECORD_ALIGNMENT - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) * adj_for_padding - adjust overlap to account for padding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) * @buf_b: second buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) * @buf_a: first buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) * @len_a: size of first buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) * @buf_a might have up to 7 bytes of padding appended. Adjust the overlap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) * accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) * Return: A pointer into @buf_b from where non-overlapped data starts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) static unsigned char *adj_for_padding(unsigned char *buf_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) unsigned char *buf_a, size_t len_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) unsigned char *p = buf_b - MAX_PADDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) unsigned char *q = buf_a + len_a - MAX_PADDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) for (i = MAX_PADDING; i; i--, p++, q++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) if (*p != *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) return p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) * intel_pt_find_overlap_tsc - determine start of non-overlapped trace data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) * using TSC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) * @buf_a: first buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) * @len_a: size of first buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) * @buf_b: second buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) * @len_b: size of second buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) * @consecutive: returns true if there is data in buf_b that is consecutive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) * to buf_a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) * If the trace contains TSC we can look at the last TSC of @buf_a and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) * first TSC of @buf_b in order to determine if the buffers overlap, and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) * walk forward in @buf_b until a later TSC is found. A precondition is that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) * @buf_a and @buf_b are positioned at a PSB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) * Return: A pointer into @buf_b from where non-overlapped data starts, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) * @buf_b + @len_b if there is no non-overlapped data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) static unsigned char *intel_pt_find_overlap_tsc(unsigned char *buf_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) size_t len_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) unsigned char *buf_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) size_t len_b, bool *consecutive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) uint64_t tsc_a, tsc_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) unsigned char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) size_t len, rem_a, rem_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) p = intel_pt_last_psb(buf_a, len_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) return buf_b; /* No PSB in buf_a => no overlap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) len = len_a - (p - buf_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) if (!intel_pt_next_tsc(p, len, &tsc_a, &rem_a)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) /* The last PSB+ in buf_a is incomplete, so go back one more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) len_a -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) p = intel_pt_last_psb(buf_a, len_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) return buf_b; /* No full PSB+ => assume no overlap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) len = len_a - (p - buf_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) if (!intel_pt_next_tsc(p, len, &tsc_a, &rem_a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) return buf_b; /* No TSC in buf_a => assume no overlap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) /* Ignore PSB+ with no TSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) if (intel_pt_next_tsc(buf_b, len_b, &tsc_b, &rem_b)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) int cmp = intel_pt_tsc_cmp(tsc_a, tsc_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) /* Same TSC, so buffers are consecutive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) if (!cmp && rem_b >= rem_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) unsigned char *start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) *consecutive = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) start = buf_b + len_b - (rem_b - rem_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) return adj_for_padding(start, buf_a, len_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) if (cmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) return buf_b; /* tsc_a < tsc_b => no overlap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) if (!intel_pt_step_psb(&buf_b, &len_b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) return buf_b + len_b; /* No PSB in buf_b => no data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) * intel_pt_find_overlap - determine start of non-overlapped trace data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) * @buf_a: first buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) * @len_a: size of first buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) * @buf_b: second buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) * @len_b: size of second buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) * @have_tsc: can use TSC packets to detect overlap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) * @consecutive: returns true if there is data in buf_b that is consecutive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) * to buf_a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) * When trace samples or snapshots are recorded there is the possibility that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) * the data overlaps. Note that, for the purposes of decoding, data is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) * useful if it begins with a PSB packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) * Return: A pointer into @buf_b from where non-overlapped data starts, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) * @buf_b + @len_b if there is no non-overlapped data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) unsigned char *intel_pt_find_overlap(unsigned char *buf_a, size_t len_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) unsigned char *buf_b, size_t len_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) bool have_tsc, bool *consecutive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) unsigned char *found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) /* Buffer 'b' must start at PSB so throw away everything before that */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) if (!intel_pt_next_psb(&buf_b, &len_b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) return buf_b + len_b; /* No PSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) if (!intel_pt_next_psb(&buf_a, &len_a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) return buf_b; /* No overlap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) if (have_tsc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) found = intel_pt_find_overlap_tsc(buf_a, len_a, buf_b, len_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) consecutive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) if (found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) return found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) * Buffer 'b' cannot end within buffer 'a' so, for comparison purposes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) * we can ignore the first part of buffer 'a'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) while (len_b < len_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) if (!intel_pt_step_psb(&buf_a, &len_a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) return buf_b; /* No overlap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) /* Now len_b >= len_a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) /* Potential overlap so check the bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) found = memmem(buf_a, len_a, buf_b, len_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) if (found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) *consecutive = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) return adj_for_padding(buf_b + len_a, buf_a, len_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) /* Try again at next PSB in buffer 'a' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) if (!intel_pt_step_psb(&buf_a, &len_a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) return buf_b; /* No overlap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) * struct fast_forward_data - data used by intel_pt_ff_cb().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) * @timestamp: timestamp to fast forward towards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) * @buf_timestamp: buffer timestamp of last buffer with trace data earlier than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) * the fast forward timestamp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) struct fast_forward_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) uint64_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) uint64_t buf_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) * intel_pt_ff_cb - fast forward lookahead callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) * @buffer: Intel PT trace buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) * @data: opaque pointer to fast forward data (struct fast_forward_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) * Determine if @buffer trace is past the fast forward timestamp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) * Return: 1 (stop lookahead) if @buffer trace is past the fast forward
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) * timestamp, and 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) static int intel_pt_ff_cb(struct intel_pt_buffer *buffer, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) struct fast_forward_data *d = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) unsigned char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) uint64_t tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) size_t rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) buf = (unsigned char *)buffer->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) len = buffer->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) if (!intel_pt_next_psb(&buf, &len) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) !intel_pt_next_tsc(buf, len, &tsc, &rem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) tsc = intel_pt_8b_tsc(tsc, buffer->ref_timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) intel_pt_log("Buffer 1st timestamp " x64_fmt " ref timestamp " x64_fmt "\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) tsc, buffer->ref_timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) * If the buffer contains a timestamp earlier that the fast forward
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) * timestamp, then record it, else stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) if (tsc < d->timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) d->buf_timestamp = buffer->ref_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) * intel_pt_fast_forward - reposition decoder forwards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) * @decoder: Intel PT decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) * @timestamp: timestamp to fast forward towards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) * Reposition decoder at the last PSB with a timestamp earlier than @timestamp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) * Return: 0 on success or negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) int intel_pt_fast_forward(struct intel_pt_decoder *decoder, uint64_t timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) struct fast_forward_data d = { .timestamp = timestamp };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) unsigned char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) intel_pt_log("Fast forward towards timestamp " x64_fmt "\n", timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) /* Find buffer timestamp of buffer to fast forward to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) err = decoder->lookahead(decoder->data, intel_pt_ff_cb, &d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) /* Walk to buffer with same buffer timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) if (d.buf_timestamp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) decoder->pos += decoder->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) decoder->len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) err = intel_pt_get_next_data(decoder, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) /* -ENOLINK means non-consecutive trace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) if (err && err != -ENOLINK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) } while (decoder->buf_timestamp != d.buf_timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) if (!decoder->buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) buf = (unsigned char *)decoder->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) len = decoder->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) if (!intel_pt_next_psb(&buf, &len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) * Walk PSBs while the PSB timestamp is less than the fast forward
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) * timestamp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) uint64_t tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) size_t rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) if (!intel_pt_next_tsc(buf, len, &tsc, &rem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) tsc = intel_pt_8b_tsc(tsc, decoder->buf_timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) * A TSC packet can slip past MTC packets but, after fast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) * forward, decoding starts at the TSC timestamp. That means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) * the timestamps may not be exactly the same as the timestamps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) * that would have been decoded without fast forward.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) if (tsc < timestamp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) intel_pt_log("Fast forward to next PSB timestamp " x64_fmt "\n", tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) decoder->pos += decoder->len - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) decoder->buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) decoder->len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) intel_pt_reposition(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) } while (intel_pt_step_psb(&buf, &len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags