Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright(C) 2015 Linaro Limited. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef INCLUDE__UTIL_PERF_CS_ETM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define INCLUDE__UTIL_PERF_CS_ETM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include "util/event.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) struct perf_session;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* Versionning header in case things need tro change in the future.  That way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * decoding of old snapshot is still possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	/* Starting with 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	CS_HEADER_VERSION_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	/* PMU->type (32 bit), total # of CPUs (32 bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	CS_PMU_TYPE_CPUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	CS_ETM_SNAPSHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	CS_HEADER_VERSION_0_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* Beginning of header common to both ETMv3 and V4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	CS_ETM_MAGIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	CS_ETM_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* ETMv3/PTM metadata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	/* Dynamic, configurable parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	CS_ETM_ETMCR = CS_ETM_CPU + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	CS_ETM_ETMTRACEIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	/* RO, taken from sysFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	CS_ETM_ETMCCER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	CS_ETM_ETMIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	CS_ETM_PRIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* ETMv4 metadata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* Dynamic, configurable parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	CS_ETMV4_TRCCONFIGR = CS_ETM_CPU + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	CS_ETMV4_TRCTRACEIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	/* RO, taken from sysFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	CS_ETMV4_TRCIDR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	CS_ETMV4_TRCIDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	CS_ETMV4_TRCIDR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	CS_ETMV4_TRCIDR8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	CS_ETMV4_TRCAUTHSTATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	CS_ETMV4_PRIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * ETMv3 exception encoding number:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * See Embedded Trace Macrocell spcification (ARM IHI 0014Q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	CS_ETMV3_EXC_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	CS_ETMV3_EXC_DEBUG_HALT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	CS_ETMV3_EXC_SMC = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	CS_ETMV3_EXC_HYP = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	CS_ETMV3_EXC_JAZELLE_THUMBEE = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	CS_ETMV3_EXC_PE_RESET = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	CS_ETMV3_EXC_UNDEFINED_INSTR = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	CS_ETMV3_EXC_SVC = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	CS_ETMV3_EXC_PREFETCH_ABORT = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	CS_ETMV3_EXC_DATA_FAULT = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	CS_ETMV3_EXC_GENERIC = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	CS_ETMV3_EXC_IRQ = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	CS_ETMV3_EXC_FIQ = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * ETMv4 exception encoding number:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * table 6-12 Possible values for the TYPE field in an Exception instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	CS_ETMV4_EXC_RESET = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	CS_ETMV4_EXC_DEBUG_HALT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	CS_ETMV4_EXC_CALL = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	CS_ETMV4_EXC_TRAP = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	CS_ETMV4_EXC_SYSTEM_ERROR = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	CS_ETMV4_EXC_INST_DEBUG = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	CS_ETMV4_EXC_DATA_DEBUG = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	CS_ETMV4_EXC_ALIGNMENT = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	CS_ETMV4_EXC_INST_FAULT = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	CS_ETMV4_EXC_DATA_FAULT = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	CS_ETMV4_EXC_IRQ = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	CS_ETMV4_EXC_FIQ = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	CS_ETMV4_EXC_END = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) enum cs_etm_sample_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	CS_ETM_EMPTY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	CS_ETM_RANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	CS_ETM_DISCONTINUITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	CS_ETM_EXCEPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	CS_ETM_EXCEPTION_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) enum cs_etm_isa {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	CS_ETM_ISA_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	CS_ETM_ISA_A64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	CS_ETM_ISA_A32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	CS_ETM_ISA_T32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct cs_etm_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct cs_etm_packet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	enum cs_etm_sample_type sample_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	enum cs_etm_isa isa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u64 start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u64 end_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 instr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u32 last_instr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u32 last_instr_subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u32 exception_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u8 last_instr_cond;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u8 last_instr_taken_branch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u8 last_instr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u8 trace_chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CS_ETM_PACKET_MAX_BUFFER 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * When working with per-thread scenarios the process under trace can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * be scheduled on any CPU and as such, more than one traceID may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * associated with the same process.  Since a traceID of '0' is illegal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * as per the CoreSight architecture, use that specific value to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * identify the queue where all packets (with any traceID) are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * aggregated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CS_ETM_PER_THREAD_TRACEID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct cs_etm_packet_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	u32 packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	u32 head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	u32 tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 instr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u64 timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u64 next_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define KiB(x) ((x) * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MiB(x) ((x) * 1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BMVAL(val, lsb, msb)	((val & GENMASK(msb, lsb)) >> lsb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_0_MAX * sizeof(u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define __perf_cs_etmv3_magic 0x3030303030303030ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define __perf_cs_etmv4_magic 0x4040404040404040ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #ifdef HAVE_CSTRACE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int cs_etm__process_auxtrace_info(union perf_event *event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				  struct perf_session *session);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int cs_etm__get_cpu(u8 trace_chan_id, int *cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int cs_etm__etmq_set_tid(struct cs_etm_queue *etmq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			 pid_t tid, u8 trace_chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 					      u8 trace_chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct cs_etm_packet_queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			      struct perf_session *session __maybe_unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline int cs_etm__get_cpu(u8 trace_chan_id __maybe_unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				  int *cpu __maybe_unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline int cs_etm__etmq_set_tid(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 				struct cs_etm_queue *etmq __maybe_unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 				pid_t tid __maybe_unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				u8 trace_chan_id __maybe_unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static inline bool cs_etm__etmq_is_timeless(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				struct cs_etm_queue *etmq __maybe_unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/* What else to return? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline void cs_etm__etmq_set_traceid_queue_timestamp(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 				struct cs_etm_queue *etmq __maybe_unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 				u8 trace_chan_id __maybe_unused) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static inline struct cs_etm_packet_queue *cs_etm__etmq_get_packet_queue(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				struct cs_etm_queue *etmq __maybe_unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				u8 trace_chan_id __maybe_unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif