Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #include "cacheline.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #include <unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifdef _SC_LEVEL1_DCACHE_LINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define cache_line_size(cacheline_sizep) *cacheline_sizep = sysconf(_SC_LEVEL1_DCACHE_LINESIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <api/fs/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "debug.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) static void cache_line_size(int *cacheline_sizep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	if (sysfs__read_int("devices/system/cpu/cpu0/cache/index0/coherency_line_size", cacheline_sizep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		pr_debug("cannot determine cache line size");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) int cacheline_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	static int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	if (!size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		cache_line_size(&size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }