Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)    edid.S: EDID data template
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)    Copyright (C) 2012 Carsten Emde <C.Emde@osadl.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)    This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)    modify it under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)    as published by the Free Software Foundation; either version 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)    of the License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)    This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)    but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)    GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)    You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)    along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* Manufacturer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MFG_LNX1 'L'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MFG_LNX2 'N'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MFG_LNX3 'X'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SERIAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define YEAR 2012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define WEEK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* EDID 1.3 standard definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define XY_RATIO_16_10	0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define XY_RATIO_4_3	0b01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define XY_RATIO_5_4	0b10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define XY_RATIO_16_9	0b11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Provide defaults for the timing bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #ifndef ESTABLISHED_TIMING1_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ESTABLISHED_TIMING1_BITS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #ifndef ESTABLISHED_TIMING2_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ESTABLISHED_TIMING2_BITS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #ifndef ESTABLISHED_TIMING3_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ESTABLISHED_TIMING3_BITS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define mfgname2id(v1,v2,v3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	((((v1-'@')&0x1f)<<10)+(((v2-'@')&0x1f)<<5)+((v3-'@')&0x1f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define swap16(v1) ((v1>>8)+((v1&0xff)<<8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define lsbs2(v1,v2) (((v1&0x0f)<<4)+(v2&0x0f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define msbs2(v1,v2) ((((v1>>8)&0x0f)<<4)+((v2>>8)&0x0f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define msbs4(v1,v2,v3,v4) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	((((v1>>8)&0x03)<<6)+(((v2>>8)&0x03)<<4)+\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	(((v3>>4)&0x03)<<2)+((v4>>4)&0x03))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define pixdpi2mm(pix,dpi) ((pix*25)/dpi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define xsize pixdpi2mm(XPIX,DPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define ysize pixdpi2mm(YPIX,DPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		.data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* Fixed header pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) header:		.byte	0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) mfg_id:		.hword	swap16(mfgname2id(MFG_LNX1, MFG_LNX2, MFG_LNX3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) prod_code:	.hword	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* Serial number. 32 bits, little endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) serial_number:	.long	SERIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* Week of manufacture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) week:		.byte	WEEK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* Year of manufacture, less 1990. (1990-2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)    If week=255, it is the model year instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) year:		.byte	YEAR-1990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) version:	.byte	VERSION 	/* EDID version, usually 1 (for 1.3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) revision:	.byte	REVISION	/* EDID revision, usually 3 (for 1.3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* If Bit 7=1	Digital input. If set, the following bit definitions apply:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)      Bits 6-1	Reserved, must be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)      Bit 0	Signal is compatible with VESA DFP 1.x TMDS CRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		  1 pixel per clock, up to 8 bits per color, MSB aligned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)    If Bit 7=0	Analog input. If clear, the following bit definitions apply:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)      Bits 6-5	Video white and sync levels, relative to blank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		  00=+0.7/-0.3 V; 01=+0.714/-0.286 V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		  10=+1.0/-0.4 V; 11=+0.7/0 V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)    Bit 4	Blank-to-black setup (pedestal) expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)    Bit 3	Separate sync supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)    Bit 2	Composite sync (on HSync) supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)    Bit 1	Sync on green supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)    Bit 0	VSync pulse must be serrated when somposite or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		  sync-on-green is used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) video_parms:	.byte	0x6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* Maximum horizontal image size, in centimetres
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)    (max 292 cm/115 in at 16:9 aspect ratio) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) max_hor_size:	.byte	xsize/10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Maximum vertical image size, in centimetres.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)    If either byte is 0, undefined (e.g. projector) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) max_vert_size:	.byte	ysize/10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Display gamma, minus 1, times 100 (range 1.00-3.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) gamma:		.byte	120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Bit 7	DPMS standby supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)    Bit 6	DPMS suspend supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)    Bit 5	DPMS active-off supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)    Bits 4-3	Display type: 00=monochrome; 01=RGB colour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		  10=non-RGB multicolour; 11=undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)    Bit 2	Standard sRGB colour space. Bytes 25-34 must contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		  sRGB standard values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)    Bit 1	Preferred timing mode specified in descriptor block 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)    Bit 0	GTF supported with default parameter values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dsp_features:	.byte	0xea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Chromaticity coordinates. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Red and green least-significant bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)    Bits 7-6	Red x value least-significant 2 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)    Bits 5-4	Red y value least-significant 2 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)    Bits 3-2	Green x value lst-significant 2 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)    Bits 1-0	Green y value least-significant 2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) red_green_lsb:	.byte	0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Blue and white least-significant 2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) blue_white_lsb:	.byte	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Red x value most significant 8 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)    0-255 encodes 0-0.996 (255/256); 0-0.999 (1023/1024) with lsbits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) red_x_msb:	.byte	0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Red y value most significant 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) red_y_msb:	.byte	0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Green x and y value most significant 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) green_x_y_msb:	.byte	0x4a,0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Blue x and y value most significant 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) blue_x_y_msb:	.byte	0x25,0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Default white point x and y value most significant 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) white_x_y_msb:	.byte	0x50,0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Established timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Bit 7	720x400 @ 70 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)    Bit 6	720x400 @ 88 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)    Bit 5	640x480 @ 60 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)    Bit 4	640x480 @ 67 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)    Bit 3	640x480 @ 72 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)    Bit 2	640x480 @ 75 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)    Bit 1	800x600 @ 56 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)    Bit 0	800x600 @ 60 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) estbl_timing1:	.byte	ESTABLISHED_TIMING1_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Bit 7	800x600 @ 72 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)    Bit 6	800x600 @ 75 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)    Bit 5	832x624 @ 75 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)    Bit 4	1024x768 @ 87 Hz, interlaced (1024x768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)    Bit 3	1024x768 @ 60 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)    Bit 2	1024x768 @ 72 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)    Bit 1	1024x768 @ 75 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)    Bit 0	1280x1024 @ 75 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) estbl_timing2:	.byte	ESTABLISHED_TIMING2_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Bit 7	1152x870 @ 75 Hz (Apple Macintosh II)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)    Bits 6-0 	Other manufacturer-specific display mod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) estbl_timing3:	.byte	ESTABLISHED_TIMING3_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Standard timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* X resolution, less 31, divided by 8 (256-2288 pixels) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) std_xres:	.byte	(XPIX/8)-31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Y resolution, X:Y pixel ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)    Bits 7-6	X:Y pixel ratio: 00=16:10; 01=4:3; 10=5:4; 11=16:9.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)    Bits 5-0	Vertical frequency, less 60 (60-123 Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) std_vres:	.byte	(XY_RATIO<<6)+VFREQ-60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.fill	7,2,0x0101	/* Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) descriptor1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Pixel clock in 10 kHz units. (0.-655.35 MHz, little-endian) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) clock:		.hword	CLOCK/10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Horizontal active pixels 8 lsbits (0-4095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) x_act_lsb:	.byte	XPIX&0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Horizontal blanking pixels 8 lsbits (0-4095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)    End of active to start of next active. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) x_blk_lsb:	.byte	XBLANK&0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Bits 7-4 	Horizontal active pixels 4 msbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)    Bits 3-0	Horizontal blanking pixels 4 msbits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) x_msbs:		.byte	msbs2(XPIX,XBLANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Vertical active lines 8 lsbits (0-4095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) y_act_lsb:	.byte	YPIX&0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Vertical blanking lines 8 lsbits (0-4095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) y_blk_lsb:	.byte	YBLANK&0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Bits 7-4 	Vertical active lines 4 msbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)    Bits 3-0 	Vertical blanking lines 4 msbits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) y_msbs:		.byte	msbs2(YPIX,YBLANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Horizontal sync offset pixels 8 lsbits (0-1023) From blanking start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) x_snc_off_lsb:	.byte	XOFFSET&0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Horizontal sync pulse width pixels 8 lsbits (0-1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) x_snc_pls_lsb:	.byte	XPULSE&0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Bits 7-4 	Vertical sync offset lines 4 lsbits (0-63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)    Bits 3-0 	Vertical sync pulse width lines 4 lsbits (0-63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) y_snc_lsb:	.byte	lsbs2(YOFFSET, YPULSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Bits 7-6 	Horizontal sync offset pixels 2 msbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)    Bits 5-4 	Horizontal sync pulse width pixels 2 msbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)    Bits 3-2 	Vertical sync offset lines 2 msbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)    Bits 1-0 	Vertical sync pulse width lines 2 msbits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) xy_snc_msbs:	.byte	msbs4(XOFFSET,XPULSE,YOFFSET,YPULSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Horizontal display size, mm, 8 lsbits (0-4095 mm, 161 in) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) x_dsp_size:	.byte	xsize&0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Vertical display size, mm, 8 lsbits (0-4095 mm, 161 in) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) y_dsp_size:	.byte	ysize&0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Bits 7-4 	Horizontal display size, mm, 4 msbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)    Bits 3-0 	Vertical display size, mm, 4 msbits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dsp_size_mbsb:	.byte	msbs2(xsize,ysize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Horizontal border pixels (each side; total is twice this) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) x_border:	.byte	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Vertical border lines (each side; total is twice this) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) y_border:	.byte	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Bit 7 	Interlaced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)    Bits 6-5 	Stereo mode: 00=No stereo; other values depend on bit 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)    Bit 0=0: 01=Field sequential, sync=1 during right; 10=similar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)      sync=1 during left; 11=4-way interleaved stereo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)    Bit 0=1 2-way interleaved stereo: 01=Right image on even lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)      10=Left image on even lines; 11=side-by-side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)    Bits 4-3 	Sync type: 00=Analog composite; 01=Bipolar analog composite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)      10=Digital composite (on HSync); 11=Digital separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)    Bit 2 	If digital separate: Vertical sync polarity (1=positive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)    Other types: VSync serrated (HSync during VSync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)    Bit 1 	If analog sync: Sync on all 3 RGB lines (else green only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)    Digital: HSync polarity (1=positive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)    Bit 0 	2-way line-interleaved stereo, if bits 4-3 are not 00. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) features:	.byte	0x18+(VSYNC_POL<<2)+(HSYNC_POL<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) descriptor2:	.byte	0,0	/* Not a detailed timing descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		.byte	0	/* Must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		.byte	0xff	/* Descriptor is monitor serial number (text) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.byte	0	/* Must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) start1:		.ascii	"Linux #0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) end1:		.byte	0x0a	/* End marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.fill	12-(end1-start1), 1, 0x20 /* Padded spaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) descriptor3:	.byte	0,0	/* Not a detailed timing descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.byte	0	/* Must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.byte	0xfd	/* Descriptor is monitor range limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.byte	0	/* Must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) start2:		.byte	VFREQ-1	/* Minimum vertical field rate (1-255 Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		.byte	VFREQ+1	/* Maximum vertical field rate (1-255 Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.byte	(CLOCK/(XPIX+XBLANK))-1 /* Minimum horizontal line rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 						    (1-255 kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.byte	(CLOCK/(XPIX+XBLANK))+1 /* Maximum horizontal line rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 						    (1-255 kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		.byte	(CLOCK/10000)+1	/* Maximum pixel clock rate, rounded up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 					   to 10 MHz multiple (10-2550 MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.byte	0	/* No extended timing information type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) end2:		.byte	0x0a	/* End marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		.fill	12-(end2-start2), 1, 0x20 /* Padded spaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) descriptor4:	.byte	0,0	/* Not a detailed timing descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.byte	0	/* Must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		.byte	0xfc	/* Descriptor is text */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.byte	0	/* Must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) start3:		.ascii	TIMING_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) end3:		.byte	0x0a	/* End marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.fill	12-(end3-start3), 1, 0x20 /* Padded spaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) extensions:	.byte	0	/* Number of extensions to follow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) checksum:	.byte	CRC	/* Sum of all bytes must be 0 */