^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Linux driver for M2Tech hiFace compatible devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2012-2013 (C) M2TECH S.r.l and Amarula Solutions B.V.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Michael Trimarchi <michael@amarulasolutions.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Antonio Ospite <ao2@amarulasolutions.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The driver is based on the work done in TerraTec DMX 6Fire USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "chip.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OUT_EP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCM_N_URBS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCM_PACKET_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCM_BUFFER_SIZE (2 * PCM_N_URBS * PCM_PACKET_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct pcm_urb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct hiface_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct urb instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct usb_anchor submitted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct pcm_substream {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct snd_pcm_substream *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bool active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) snd_pcm_uframes_t dma_off; /* current position in alsa dma_area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) snd_pcm_uframes_t period_off; /* current position in current period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum { /* pcm streaming states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) STREAM_DISABLED, /* no pcm streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) STREAM_STARTING, /* pcm streaming requested, waiting to become ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) STREAM_RUNNING, /* pcm streaming running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) STREAM_STOPPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct pcm_runtime {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct hiface_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct snd_pcm *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct pcm_substream playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) bool panic; /* if set driver won't do anymore pcm on device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct pcm_urb out_urbs[PCM_N_URBS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct mutex stream_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 stream_state; /* one of STREAM_XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 extra_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) wait_queue_head_t stream_wait_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bool stream_wait_cond;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const unsigned int rates[] = { 44100, 48000, 88200, 96000, 176400, 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 352800, 384000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct snd_pcm_hw_constraint_list constraints_extra_rates = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .count = ARRAY_SIZE(rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .list = rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct snd_pcm_hardware pcm_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SNDRV_PCM_INFO_BATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .formats = SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .rates = SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SNDRV_PCM_RATE_96000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SNDRV_PCM_RATE_176400 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SNDRV_PCM_RATE_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .rate_min = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .rate_max = 192000, /* changes in hiface_pcm_open to support extra rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .buffer_bytes_max = PCM_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .period_bytes_min = PCM_PACKET_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .period_bytes_max = PCM_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .periods_max = 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* message values used to change the sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HIFACE_SET_RATE_REQUEST 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HIFACE_RATE_44100 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HIFACE_RATE_48000 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HIFACE_RATE_88200 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HIFACE_RATE_96000 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HIFACE_RATE_176400 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HIFACE_RATE_192000 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HIFACE_RATE_352800 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HIFACE_RATE_384000 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int hiface_pcm_set_rate(struct pcm_runtime *rt, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct usb_device *device = rt->chip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u16 rate_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* We are already sure that the rate is supported here thanks to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * ALSA constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) rate_value = HIFACE_RATE_44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) rate_value = HIFACE_RATE_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) rate_value = HIFACE_RATE_88200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) rate_value = HIFACE_RATE_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case 176400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) rate_value = HIFACE_RATE_176400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) rate_value = HIFACE_RATE_192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case 352800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) rate_value = HIFACE_RATE_352800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case 384000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) rate_value = HIFACE_RATE_384000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_err(&device->dev, "Unsupported rate %d\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * USBIO: Vendor 0xb0(wValue=0x0043, wIndex=0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * 43 b0 43 00 00 00 00 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * USBIO: Vendor 0xb0(wValue=0x004b, wIndex=0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * 43 b0 4b 00 00 00 00 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * This control message doesn't have any ack from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * other side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = usb_control_msg_send(device, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) HIFACE_SET_RATE_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_OTHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rate_value, 0, NULL, 0, 100, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_err(&device->dev, "Error setting samplerate %d.\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct pcm_substream *hiface_pcm_get_substream(struct snd_pcm_substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *alsa_sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct pcm_runtime *rt = snd_pcm_substream_chip(alsa_sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct device *device = &rt->chip->dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (alsa_sub->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return &rt->playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_err(device, "Error getting pcm substream slot.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* call with stream_mutex locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void hiface_pcm_stream_stop(struct pcm_runtime *rt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int i, time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (rt->stream_state != STREAM_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rt->stream_state = STREAM_STOPPING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) for (i = 0; i < PCM_N_URBS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) time = usb_wait_anchor_empty_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) &rt->out_urbs[i].submitted, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) usb_kill_anchored_urbs(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) &rt->out_urbs[i].submitted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) usb_kill_urb(&rt->out_urbs[i].instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) rt->stream_state = STREAM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* call with stream_mutex locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int hiface_pcm_stream_start(struct pcm_runtime *rt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (rt->stream_state == STREAM_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* reset panic state when starting a new stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rt->panic = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* submit our out urbs zero init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) rt->stream_state = STREAM_STARTING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for (i = 0; i < PCM_N_URBS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) memset(rt->out_urbs[i].buffer, 0, PCM_PACKET_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) usb_anchor_urb(&rt->out_urbs[i].instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) &rt->out_urbs[i].submitted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = usb_submit_urb(&rt->out_urbs[i].instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) hiface_pcm_stream_stop(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* wait for first out urb to return (sent in in urb handler) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) wait_event_timeout(rt->stream_wait_queue, rt->stream_wait_cond,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (rt->stream_wait_cond) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct device *device = &rt->chip->dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_dbg(device, "%s: Stream is running wakeup event\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) rt->stream_state = STREAM_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) hiface_pcm_stream_stop(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* The hardware wants word-swapped 32-bit values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void memcpy_swahw32(u8 *dest, u8 *src, unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) for (i = 0; i < n / 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ((u32 *)dest)[i] = swahw32(((u32 *)src)[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* call with substream locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* returns true if a period elapsed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static bool hiface_pcm_playback(struct pcm_substream *sub, struct pcm_urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct snd_pcm_runtime *alsa_rt = sub->instance->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct device *device = &urb->chip->dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u8 *source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int pcm_buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) WARN_ON(alsa_rt->format != SNDRV_PCM_FORMAT_S32_LE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pcm_buffer_size = snd_pcm_lib_buffer_bytes(sub->instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (sub->dma_off + PCM_PACKET_SIZE <= pcm_buffer_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_dbg(device, "%s: (1) buffer_size %#x dma_offset %#x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) (unsigned int) pcm_buffer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) (unsigned int) sub->dma_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) source = alsa_rt->dma_area + sub->dma_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) memcpy_swahw32(urb->buffer, source, PCM_PACKET_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* wrap around at end of ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_dbg(device, "%s: (2) buffer_size %#x dma_offset %#x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) (unsigned int) pcm_buffer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (unsigned int) sub->dma_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) len = pcm_buffer_size - sub->dma_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) source = alsa_rt->dma_area + sub->dma_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) memcpy_swahw32(urb->buffer, source, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) source = alsa_rt->dma_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) memcpy_swahw32(urb->buffer + len, source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PCM_PACKET_SIZE - len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) sub->dma_off += PCM_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (sub->dma_off >= pcm_buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) sub->dma_off -= pcm_buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) sub->period_off += PCM_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (sub->period_off >= alsa_rt->period_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) sub->period_off %= alsa_rt->period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void hiface_pcm_out_urb_handler(struct urb *usb_urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct pcm_urb *out_urb = usb_urb->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct pcm_runtime *rt = out_urb->chip->pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct pcm_substream *sub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) bool do_period_elapsed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (rt->panic || rt->stream_state == STREAM_STOPPING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (unlikely(usb_urb->status == -ENOENT || /* unlinked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) usb_urb->status == -ENODEV || /* device removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) usb_urb->status == -ECONNRESET || /* unlinked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) usb_urb->status == -ESHUTDOWN)) { /* device disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) goto out_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (rt->stream_state == STREAM_STARTING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) rt->stream_wait_cond = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) wake_up(&rt->stream_wait_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* now send our playback data (if a free out urb was found) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) sub = &rt->playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) spin_lock_irqsave(&sub->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (sub->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) do_period_elapsed = hiface_pcm_playback(sub, out_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) memset(out_urb->buffer, 0, PCM_PACKET_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) spin_unlock_irqrestore(&sub->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (do_period_elapsed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) snd_pcm_period_elapsed(sub->instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = usb_submit_urb(&out_urb->instance, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) goto out_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) out_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) rt->panic = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int hiface_pcm_open(struct snd_pcm_substream *alsa_sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct pcm_runtime *rt = snd_pcm_substream_chip(alsa_sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct pcm_substream *sub = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct snd_pcm_runtime *alsa_rt = alsa_sub->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (rt->panic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) mutex_lock(&rt->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) alsa_rt->hw = pcm_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (alsa_sub->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) sub = &rt->playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!sub) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct device *device = &rt->chip->dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mutex_unlock(&rt->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_err(device, "Invalid stream type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (rt->extra_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) alsa_rt->hw.rates |= SNDRV_PCM_RATE_KNOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) alsa_rt->hw.rate_max = 384000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* explicit constraints needed as we added SNDRV_PCM_RATE_KNOT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = snd_pcm_hw_constraint_list(alsa_sub->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) &constraints_extra_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mutex_unlock(&rt->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) sub->instance = alsa_sub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) sub->active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) mutex_unlock(&rt->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int hiface_pcm_close(struct snd_pcm_substream *alsa_sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct pcm_runtime *rt = snd_pcm_substream_chip(alsa_sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct pcm_substream *sub = hiface_pcm_get_substream(alsa_sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (rt->panic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mutex_lock(&rt->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (sub) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) hiface_pcm_stream_stop(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* deactivate substream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) spin_lock_irqsave(&sub->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) sub->instance = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) sub->active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) spin_unlock_irqrestore(&sub->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mutex_unlock(&rt->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int hiface_pcm_prepare(struct snd_pcm_substream *alsa_sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct pcm_runtime *rt = snd_pcm_substream_chip(alsa_sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct pcm_substream *sub = hiface_pcm_get_substream(alsa_sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct snd_pcm_runtime *alsa_rt = alsa_sub->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (rt->panic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) mutex_lock(&rt->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) hiface_pcm_stream_stop(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) sub->dma_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) sub->period_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (rt->stream_state == STREAM_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = hiface_pcm_set_rate(rt, alsa_rt->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) mutex_unlock(&rt->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = hiface_pcm_stream_start(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mutex_unlock(&rt->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mutex_unlock(&rt->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int hiface_pcm_trigger(struct snd_pcm_substream *alsa_sub, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct pcm_substream *sub = hiface_pcm_get_substream(alsa_sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct pcm_runtime *rt = snd_pcm_substream_chip(alsa_sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (rt->panic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) spin_lock_irq(&sub->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) sub->active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) spin_unlock_irq(&sub->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) spin_lock_irq(&sub->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) sub->active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) spin_unlock_irq(&sub->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static snd_pcm_uframes_t hiface_pcm_pointer(struct snd_pcm_substream *alsa_sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct pcm_substream *sub = hiface_pcm_get_substream(alsa_sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct pcm_runtime *rt = snd_pcm_substream_chip(alsa_sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) snd_pcm_uframes_t dma_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (rt->panic || !sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return SNDRV_PCM_POS_XRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) spin_lock_irqsave(&sub->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dma_offset = sub->dma_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) spin_unlock_irqrestore(&sub->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return bytes_to_frames(alsa_sub->runtime, dma_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static const struct snd_pcm_ops pcm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .open = hiface_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .close = hiface_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .prepare = hiface_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .trigger = hiface_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .pointer = hiface_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int hiface_pcm_init_urb(struct pcm_urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct hiface_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned int ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) void (*handler)(struct urb *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) urb->chip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) usb_init_urb(&urb->instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) urb->buffer = kzalloc(PCM_PACKET_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (!urb->buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) usb_fill_bulk_urb(&urb->instance, chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) usb_sndbulkpipe(chip->dev, ep), (void *)urb->buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PCM_PACKET_SIZE, handler, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (usb_urb_ep_type_check(&urb->instance))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) init_usb_anchor(&urb->submitted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) void hiface_pcm_abort(struct hiface_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct pcm_runtime *rt = chip->pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (rt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) rt->panic = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) mutex_lock(&rt->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) hiface_pcm_stream_stop(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mutex_unlock(&rt->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void hiface_pcm_destroy(struct hiface_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct pcm_runtime *rt = chip->pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) for (i = 0; i < PCM_N_URBS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) kfree(rt->out_urbs[i].buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) kfree(chip->pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) chip->pcm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static void hiface_pcm_free(struct snd_pcm *pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct pcm_runtime *rt = pcm->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (rt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) hiface_pcm_destroy(rt->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int hiface_pcm_init(struct hiface_chip *chip, u8 extra_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct pcm_runtime *rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) rt = kzalloc(sizeof(*rt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!rt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) rt->chip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) rt->stream_state = STREAM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (extra_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) rt->extra_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) init_waitqueue_head(&rt->stream_wait_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) mutex_init(&rt->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) spin_lock_init(&rt->playback.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) for (i = 0; i < PCM_N_URBS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = hiface_pcm_init_urb(&rt->out_urbs[i], chip, OUT_EP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) hiface_pcm_out_urb_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = snd_pcm_new(chip->card, "USB-SPDIF Audio", 0, 1, 0, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_err(&chip->dev->dev, "Cannot create pcm instance\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pcm->private_data = rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pcm->private_free = hiface_pcm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) strlcpy(pcm->name, "USB-SPDIF Audio", sizeof(pcm->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_VMALLOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) rt->instance = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) chip->pcm = rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) for (i = 0; i < PCM_N_URBS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) kfree(rt->out_urbs[i].buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) kfree(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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