^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the AT73C213 16-bit stereo DAC on Atmel ATSTK1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 - 2007 Atmel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SND_AT73C213_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SND_AT73C213_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* DAC control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DAC_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DAC_CTRL_ONPADRV 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DAC_CTRL_ONAUXIN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DAC_CTRL_ONDACR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DAC_CTRL_ONDACL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DAC_CTRL_ONLNOR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DAC_CTRL_ONLNOL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DAC_CTRL_ONLNIR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DAC_CTRL_ONLNIL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* DAC left line in gain register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DAC_LLIG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DAC_LLIG_LLIG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* DAC right line in gain register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DAC_RLIG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DAC_RLIG_RLIG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* DAC Left Master Playback Gain Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DAC_LMPG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DAC_LMPG_LMPG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* DAC Right Master Playback Gain Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DAC_RMPG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DAC_RMPG_RMPG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* DAC Left Line Out Gain Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DAC_LLOG 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DAC_LLOG_LLOG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* DAC Right Line Out Gain Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DAC_RLOG 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DAC_RLOG_RLOG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* DAC Output Level Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DAC_OLC 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DAC_OLC_RSHORT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DAC_OLC_ROLC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DAC_OLC_LSHORT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DAC_OLC_LOLC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* DAC Mixer Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DAC_MC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DAC_MC_INVR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DAC_MC_INVL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DAC_MC_RMSMIN2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DAC_MC_RMSMIN1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DAC_MC_LMSMIN2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DAC_MC_LMSMIN1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* DAC Clock and Sampling Frequency Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DAC_CSFC 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DAC_CSFC_OVRSEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* DAC Miscellaneous Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DAC_MISC 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DAC_MISC_VCMCAPSEL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DAC_MISC_DINTSEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DAC_MISC_DITHEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DAC_MISC_DEEMPEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DAC_MISC_NBITS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* DAC Precharge Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DAC_PRECH 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DAC_PRECH_PRCHGPDRV 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DAC_PRECH_PRCHGAUX1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DAC_PRECH_PRCHGLNOR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DAC_PRECH_PRCHGLNOL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DAC_PRECH_PRCHGLNIR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DAC_PRECH_PRCHGLNIL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DAC_PRECH_PRCHG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DAC_PRECH_ONMSTR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* DAC Auxiliary Input Gain Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DAC_AUXG 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DAC_AUXG_AUXG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* DAC Reset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DAC_RST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DAC_RST_RESMASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DAC_RST_RESFILZ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DAC_RST_RSTZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Power Amplifier Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PA_CTRL 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PA_CTRL_APAON 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PA_CTRL_APAPRECH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PA_CTRL_APALP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PA_CTRL_APAGAIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif /* _SND_AT73C213_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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