^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for CS4231 sound chips found on Sparcs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based entirely upon drivers/sbus/audio/cs4231.c which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1996, 1997, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and also sound/isa/cs423x/cs4231_lib.c which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifdef CONFIG_SBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SBUS_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EBUS_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/ebus_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Enable this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MODULE_DESCRIPTION("Sun CS4231");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #ifdef SBUS_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct sbus_dma_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) spinlock_t lock; /* DMA access lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct snd_cs4231;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct cs4231_dma_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void (*prepare)(struct cs4231_dma_control *dma_cont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void (*enable)(struct cs4231_dma_control *dma_cont, int on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int (*request)(struct cs4231_dma_control *dma_cont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dma_addr_t bus_addr, size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int (*address)(struct cs4231_dma_control *dma_cont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #ifdef EBUS_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct ebus_dma_info ebus_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifdef SBUS_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct sbus_dma_info sbus_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct snd_cs4231 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) spinlock_t lock; /* registers access lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void __iomem *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct cs4231_dma_control p_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct cs4231_dma_control c_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CS4231_FLAG_EBUS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CS4231_FLAG_PLAYBACK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CS4231_FLAG_CAPTURE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct snd_pcm_substream *playback_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int p_periods_sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct snd_pcm_substream *capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int c_periods_sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct snd_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned short mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CS4231_MODE_NONE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CS4231_MODE_PLAY 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CS4231_MODE_RECORD 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CS4231_MODE_TIMER 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CS4231_MODE_OPEN (CS4231_MODE_PLAY | CS4231_MODE_RECORD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) CS4231_MODE_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned char image[32]; /* registers image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int mce_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int calibrate_mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct mutex mce_mutex; /* mutex for mce register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct mutex open_mutex; /* mutex for ALSA open/close */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct platform_device *op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int irq[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int regs_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct snd_cs4231 *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * now.... -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* IO ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #include <sound/cs4231-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* XXX offsets are different than PC ISA chips... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CS4231U(chip, x) ((chip)->port + ((c_d_c_CS4231##x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* SBUS DMA register defines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define APCCSR 0x10UL /* APC DMA CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define APCCVA 0x20UL /* APC Capture DMA Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define APCCC 0x24UL /* APC Capture Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define APCCNVA 0x28UL /* APC Capture DMA Next Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define APCCNC 0x2cUL /* APC Capture Next Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define APCPVA 0x30UL /* APC Play DMA Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define APCPC 0x34UL /* APC Play Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define APCPNVA 0x38UL /* APC Play DMA Next Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define APCPNC 0x3cUL /* APC Play Next Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Defines for SBUS DMA-routines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define APCVA 0x0UL /* APC DMA Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define APCC 0x4UL /* APC Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define APCNVA 0x8UL /* APC DMA Next Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define APCNC 0xcUL /* APC Next Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define APC_PLAY 0x30UL /* Play registers start at 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define APC_RECORD 0x20UL /* Record registers start at 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* APCCSR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define APC_PLAY_INT 0x400000 /* Playback interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define APC_CAPT_INT 0x200000 /* Capture interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define APC_GENL_INT 0x100000 /* General interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define APC_XINT_ENA 0x80000 /* General ext int. enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define APC_XINT_PLAY 0x40000 /* Playback ext intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define APC_XINT_CAPT 0x20000 /* Capture ext intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define APC_XINT_GENL 0x10000 /* Error ext intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define APC_PPAUSE 0x80 /* Pause the play DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define APC_CPAUSE 0x40 /* Pause the capture DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define APC_CDC_RESET 0x20 /* CODEC RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define APC_PDMA_READY 0x08 /* Play DMA Go */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define APC_CDMA_READY 0x04 /* Capture DMA Go */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define APC_CHIP_RESET 0x01 /* Reset the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* EBUS DMA register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define EBDMA_CSR 0x00UL /* Control/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define EBDMA_ADDR 0x04UL /* DMA Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define EBDMA_COUNT 0x08UL /* DMA Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Some variables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const unsigned char freq_bits[14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* 5510 */ 0x00 | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* 6620 */ 0x0E | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* 8000 */ 0x00 | CS4231_XTAL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* 9600 */ 0x0E | CS4231_XTAL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* 11025 */ 0x02 | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* 16000 */ 0x02 | CS4231_XTAL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* 18900 */ 0x04 | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* 22050 */ 0x06 | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* 27042 */ 0x04 | CS4231_XTAL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* 32000 */ 0x06 | CS4231_XTAL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* 33075 */ 0x0C | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* 37800 */ 0x08 | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* 44100 */ 0x0A | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* 48000 */ 0x0C | CS4231_XTAL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const unsigned int rates[14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 27042, 32000, 33075, 37800, 44100, 48000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .count = ARRAY_SIZE(rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .list = rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return snd_pcm_hw_constraint_list(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) &hw_constraints_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const unsigned char snd_cs4231_original_image[32] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 0x00, /* 00/00 - lic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0x00, /* 01/01 - ric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 0x9f, /* 02/02 - la1ic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 0x9f, /* 03/03 - ra1ic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0x9f, /* 04/04 - la2ic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 0x9f, /* 05/05 - ra2ic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 0xbf, /* 06/06 - loc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0xbf, /* 07/07 - roc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 0x20, /* 08/08 - pdfr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) CS4231_AUTOCALIB, /* 09/09 - ic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 0x00, /* 0a/10 - pc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 0x00, /* 0b/11 - ti */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CS4231_MODE2, /* 0c/12 - mi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 0x00, /* 0d/13 - lbc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 0x00, /* 0e/14 - pbru */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 0x00, /* 0f/15 - pbrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 0x80, /* 10/16 - afei */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0x01, /* 11/17 - afeii */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 0x9f, /* 12/18 - llic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 0x9f, /* 13/19 - rlic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 0x00, /* 14/20 - tlb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0x00, /* 15/21 - thb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 0x00, /* 16/22 - la3mic/reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 0x00, /* 17/23 - ra3mic/reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 0x00, /* 18/24 - afs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 0x00, /* 19/25 - lamoc/version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 0x00, /* 1a/26 - mioc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0x00, /* 1b/27 - ramoc/reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 0x20, /* 1c/28 - cdfr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 0x00, /* 1d/29 - res4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 0x00, /* 1e/30 - cbru */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0x00, /* 1f/31 - cbrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (cp->flags & CS4231_FLAG_EBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return readb(reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return sbus_readb(reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) void __iomem *reg_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (cp->flags & CS4231_FLAG_EBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return writeb(val, reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return sbus_writeb(val, reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Basic I/O functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void snd_cs4231_ready(struct snd_cs4231 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) for (timeout = 250; timeout > 0; timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if ((val & CS4231_INIT) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) snd_cs4231_ready(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) snd_printdd("out: auto calibration time out - reg = 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "value = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) __cs4231_writeb(chip, value, CS4231U(chip, REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static inline void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned char mask, unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned char tmp = (chip->image[reg] & mask) | value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) chip->image[reg] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!chip->calibrate_mute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) snd_cs4231_dout(chip, reg, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) snd_cs4231_dout(chip, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) chip->image[reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) snd_cs4231_ready(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) snd_printdd("in: auto calibration time out - reg = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return __cs4231_readb(chip, CS4231U(chip, REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * CS4231 detection / MCE routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* looks like this sequence is proper for CS4231A chip (GUS MAX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) for (timeout = 5; timeout > 0; timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __cs4231_readb(chip, CS4231U(chip, REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* end of cleanup sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) for (timeout = 500; timeout > 0; timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if ((val & CS4231_INIT) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) snd_cs4231_ready(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) snd_printdd("mce_up - auto calibration time out (0)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) chip->mce_bit |= CS4231_MCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) timeout = __cs4231_readb(chip, CS4231U(chip, REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (timeout == 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) snd_printdd("mce_up [%p]: serious init problem - "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "codec still busy\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) chip->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (!(timeout & CS4231_MCE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) CS4231U(chip, REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned long flags, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) snd_cs4231_busy_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) snd_printdd("mce_down [%p] - auto calibration time out (0)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) CS4231U(chip, REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) chip->mce_bit &= ~CS4231_MCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) reg = __cs4231_readb(chip, CS4231U(chip, REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) __cs4231_writeb(chip, chip->mce_bit | (reg & 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) CS4231U(chip, REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (reg == 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) snd_printdd("mce_down [%p]: serious init problem "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "- codec still busy\n", chip->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if ((reg & CS4231_MCE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * Wait for auto-calibration (AC) process to finish, i.e. ACI to go low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) timeout = jiffies + msecs_to_jiffies(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) reg = snd_cs4231_in(chip, CS4231_TEST_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) reg &= CS4231_CALIB_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) } while (reg && time_before(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) snd_printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "mce_down - auto calibration time out (2)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned int *periods_sent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int period_size = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int offset = period_size * (*periods_sent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (WARN_ON(period_size >= (1 << 24)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (dma_cont->request(dma_cont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) runtime->dma_addr + offset, period_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void cs4231_dma_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int what, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct cs4231_dma_control *dma_cont;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (what & CS4231_PLAYBACK_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dma_cont = &chip->p_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dma_cont->prepare(dma_cont, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dma_cont->enable(dma_cont, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) snd_cs4231_advance_dma(dma_cont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) chip->playback_substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) &chip->p_periods_sent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dma_cont->enable(dma_cont, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (what & CS4231_RECORD_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dma_cont = &chip->c_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dma_cont->prepare(dma_cont, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dma_cont->enable(dma_cont, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) snd_cs4231_advance_dma(dma_cont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) chip->capture_substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) &chip->c_periods_sent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dma_cont->enable(dma_cont, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int what = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (s == chip->playback_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) what |= CS4231_PLAYBACK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) } else if (s == chip->capture_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) what |= CS4231_RECORD_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (cmd == SNDRV_PCM_TRIGGER_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) cs4231_dma_trigger(substream, what, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) chip->image[CS4231_IFACE_CTRL] |= what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) cs4231_dma_trigger(substream, what, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) chip->image[CS4231_IFACE_CTRL] &= ~what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) snd_cs4231_out(chip, CS4231_IFACE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) chip->image[CS4231_IFACE_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * CODEC I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static unsigned char snd_cs4231_get_rate(unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) for (i = 0; i < 14; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (rate == rates[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return freq_bits[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return freq_bits[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned char rformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) rformat = CS4231_LINEAR_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) switch (format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case SNDRV_PCM_FORMAT_MU_LAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) rformat = CS4231_ULAW_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case SNDRV_PCM_FORMAT_A_LAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) rformat = CS4231_ALAW_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) rformat = CS4231_LINEAR_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case SNDRV_PCM_FORMAT_S16_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) rformat = CS4231_LINEAR_16_BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case SNDRV_PCM_FORMAT_IMA_ADPCM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) rformat = CS4231_ADPCM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (channels > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) rformat |= CS4231_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return rformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mute = mute ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (chip->calibrate_mute == mute) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (!mute) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) chip->image[CS4231_LEFT_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) chip->image[CS4231_RIGHT_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) snd_cs4231_dout(chip, CS4231_LOOPBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) chip->image[CS4231_LOOPBACK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) snd_cs4231_dout(chip, CS4231_MONO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) chip->calibrate_mute = mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned char pdfr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mutex_lock(&chip->mce_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) snd_cs4231_calibrate_mute(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) snd_cs4231_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) pdfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) snd_cs4231_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) snd_cs4231_calibrate_mute(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) mutex_unlock(&chip->mce_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned char cdfr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) mutex_lock(&chip->mce_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) snd_cs4231_calibrate_mute(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) snd_cs4231_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) (cdfr & 0x0f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) snd_cs4231_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) snd_cs4231_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) snd_cs4231_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) snd_cs4231_calibrate_mute(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) mutex_unlock(&chip->mce_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * Timer interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct snd_cs4231 *chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int snd_cs4231_timer_start(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) unsigned int ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct snd_cs4231 *chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ticks = timer->sticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) snd_cs4231_out(chip, CS4231_TIMER_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) chip->image[CS4231_TIMER_HIGH] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) (unsigned char) (ticks >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) snd_cs4231_out(chip, CS4231_TIMER_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) chip->image[CS4231_TIMER_LOW] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) (unsigned char) ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) chip->image[CS4231_ALT_FEATURE_1] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) CS4231_TIMER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int snd_cs4231_timer_stop(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct snd_cs4231 *chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) chip->image[CS4231_ALT_FEATURE_1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static void snd_cs4231_init(struct snd_cs4231 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) snd_cs4231_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #ifdef SNDRV_DEBUG_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) snd_printdd("init: (1)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) snd_cs4231_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) CS4231_PLAYBACK_PIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) CS4231_RECORD_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) CS4231_RECORD_PIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) CS4231_CALIB_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) snd_cs4231_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #ifdef SNDRV_DEBUG_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) snd_printdd("init: (2)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) snd_cs4231_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) chip->image[CS4231_ALT_FEATURE_1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) snd_cs4231_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #ifdef SNDRV_DEBUG_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) snd_printdd("init: (3) - afei = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) chip->image[CS4231_ALT_FEATURE_1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) snd_cs4231_out(chip, CS4231_ALT_FEATURE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) chip->image[CS4231_ALT_FEATURE_2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) snd_cs4231_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) chip->image[CS4231_PLAYBK_FORMAT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) snd_cs4231_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #ifdef SNDRV_DEBUG_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) snd_printdd("init: (4)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) snd_cs4231_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) snd_cs4231_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #ifdef SNDRV_DEBUG_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) snd_printdd("init: (5)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mutex_lock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if ((chip->mode & mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mutex_unlock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (chip->mode & CS4231_MODE_OPEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) chip->mode |= mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) mutex_unlock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* ok. now enable and ack CODEC IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) CS4231_RECORD_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) CS4231_TIMER_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) CS4231_RECORD_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) CS4231_TIMER_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) chip->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) mutex_unlock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) mutex_lock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) chip->mode &= ~mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (chip->mode & CS4231_MODE_OPEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mutex_unlock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) snd_cs4231_calibrate_mute(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* disable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* now disable record & playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (chip->image[CS4231_IFACE_CTRL] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) snd_cs4231_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) chip->image[CS4231_IFACE_CTRL] &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) snd_cs4231_out(chip, CS4231_IFACE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) chip->image[CS4231_IFACE_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) snd_cs4231_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* clear IRQ again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) snd_cs4231_calibrate_mute(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) chip->mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) mutex_unlock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * timer open/close
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static int snd_cs4231_timer_open(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct snd_cs4231 *chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) snd_cs4231_open(chip, CS4231_MODE_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static int snd_cs4231_timer_close(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct snd_cs4231 *chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) snd_cs4231_close(chip, CS4231_MODE_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static const struct snd_timer_hardware snd_cs4231_timer_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .flags = SNDRV_TIMER_HW_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .resolution = 9945,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .ticks = 65535,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .open = snd_cs4231_timer_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .close = snd_cs4231_timer_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .c_resolution = snd_cs4231_timer_resolution,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .start = snd_cs4231_timer_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .stop = snd_cs4231_timer_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * ok.. exported functions..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) unsigned char new_pdfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) params_channels(hw_params)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) snd_cs4231_get_rate(params_rate(hw_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) snd_cs4231_playback_format(chip, hw_params, new_pdfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) CS4231_PLAYBACK_PIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (WARN_ON(runtime->period_size > 0xffff + 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) chip->p_periods_sent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) unsigned char new_cdfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) params_channels(hw_params)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) snd_cs4231_get_rate(params_rate(hw_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) snd_cs4231_capture_format(chip, hw_params, new_cdfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) CS4231_RECORD_PIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) chip->c_periods_sent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static void snd_cs4231_overrange(struct snd_cs4231 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) unsigned char res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) res = snd_cs4231_in(chip, CS4231_TEST_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* detect overrange only above 0dB; may be user selectable? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (res & (0x08 | 0x02))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) chip->capture_substream->runtime->overrange++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static void snd_cs4231_play_callback(struct snd_cs4231 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) snd_pcm_period_elapsed(chip->playback_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) &chip->p_periods_sent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static void snd_cs4231_capture_callback(struct snd_cs4231 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) snd_pcm_period_elapsed(chip->capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) &chip->c_periods_sent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static snd_pcm_uframes_t snd_cs4231_playback_pointer(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct cs4231_dma_control *dma_cont = &chip->p_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ptr = dma_cont->address(dma_cont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (ptr != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ptr -= substream->runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static snd_pcm_uframes_t snd_cs4231_capture_pointer(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct cs4231_dma_control *dma_cont = &chip->c_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ptr = dma_cont->address(dma_cont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (ptr != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ptr -= substream->runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int snd_cs4231_probe(struct snd_cs4231 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) int vers = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) unsigned char *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) for (i = 0; i < 50; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) msleep(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) vers = snd_cs4231_in(chip, CS4231_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (id == 0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) break; /* this is valid value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (id != 0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return -ENODEV; /* no valid device found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* clear any pendings IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) __cs4231_readb(chip, CS4231U(chip, STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) __cs4231_writeb(chip, 0, CS4231U(chip, STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) chip->image[CS4231_IFACE_CTRL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) chip->image[CS4231_ALT_FEATURE_1] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) chip->image[CS4231_ALT_FEATURE_2] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (vers & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ptr = (unsigned char *) &chip->image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) snd_cs4231_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) snd_cs4231_out(chip, i, *ptr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) snd_cs4231_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) snd_cs4231_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return 0; /* all things are ok.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static const struct snd_pcm_hardware snd_cs4231_playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) SNDRV_PCM_INFO_SYNC_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .formats = SNDRV_PCM_FMTBIT_MU_LAW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) SNDRV_PCM_FMTBIT_A_LAW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) SNDRV_PCM_FMTBIT_IMA_ADPCM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) SNDRV_PCM_FMTBIT_U8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) SNDRV_PCM_FMTBIT_S16_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .rates = SNDRV_PCM_RATE_KNOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .rate_min = 5510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .buffer_bytes_max = 32 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .period_bytes_max = 32 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static const struct snd_pcm_hardware snd_cs4231_capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) SNDRV_PCM_INFO_SYNC_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .formats = SNDRV_PCM_FMTBIT_MU_LAW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) SNDRV_PCM_FMTBIT_A_LAW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) SNDRV_PCM_FMTBIT_IMA_ADPCM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) SNDRV_PCM_FMTBIT_U8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) SNDRV_PCM_FMTBIT_S16_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .rates = SNDRV_PCM_RATE_KNOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .rate_min = 5510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .buffer_bytes_max = 32 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .period_bytes_max = 32 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) runtime->hw = snd_cs4231_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) err = snd_cs4231_open(chip, CS4231_MODE_PLAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) chip->playback_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) chip->p_periods_sent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) snd_cs4231_xrate(runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) runtime->hw = snd_cs4231_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) err = snd_cs4231_open(chip, CS4231_MODE_RECORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) chip->capture_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) chip->c_periods_sent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) snd_cs4231_xrate(runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) snd_cs4231_close(chip, CS4231_MODE_PLAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) chip->playback_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) snd_cs4231_close(chip, CS4231_MODE_RECORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) chip->capture_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* XXX We can do some power-management, in particular on EBUS using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * XXX the audio AUXIO register...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static const struct snd_pcm_ops snd_cs4231_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .open = snd_cs4231_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .close = snd_cs4231_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .hw_params = snd_cs4231_playback_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .prepare = snd_cs4231_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .trigger = snd_cs4231_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .pointer = snd_cs4231_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static const struct snd_pcm_ops snd_cs4231_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .open = snd_cs4231_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .close = snd_cs4231_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .hw_params = snd_cs4231_capture_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .prepare = snd_cs4231_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .trigger = snd_cs4231_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .pointer = snd_cs4231_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static int snd_cs4231_pcm(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct snd_cs4231 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) err = snd_pcm_new(card, "CS4231", 0, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) &snd_cs4231_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) &snd_cs4231_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* global setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) strcpy(pcm->name, "CS4231");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) &chip->op->dev, 64 * 1024, 128 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) chip->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static int snd_cs4231_timer(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct snd_cs4231 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct snd_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct snd_timer_id tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* Timer initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) tid.dev_class = SNDRV_TIMER_CLASS_CARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) tid.card = card->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) tid.device = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) tid.subdevice = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) err = snd_timer_new(card, "CS4231", &tid, &timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) strcpy(timer->name, "CS4231");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) timer->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) timer->hw = snd_cs4231_timer_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) chip->timer = timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * MIXER part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static const char * const texts[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) "Line", "CD", "Mic", "Mix"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return snd_ctl_enum_info(uinfo, 2, 4, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) ucontrol->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ucontrol->value.enumerated.item[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) unsigned short left, right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (ucontrol->value.enumerated.item[0] > 3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ucontrol->value.enumerated.item[1] > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) left = ucontrol->value.enumerated.item[0] << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) right = ucontrol->value.enumerated.item[1] << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) change = left != chip->image[CS4231_LEFT_INPUT] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) right != chip->image[CS4231_RIGHT_INPUT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) int mask = (kcontrol->private_value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) uinfo->type = (mask == 1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) uinfo->value.integer.max = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) int reg = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) int shift = (kcontrol->private_value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) int mask = (kcontrol->private_value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) int invert = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) (mask - ucontrol->value.integer.value[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) int reg = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) int shift = (kcontrol->private_value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) int mask = (kcontrol->private_value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) int invert = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) val = (ucontrol->value.integer.value[0] & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) val = mask - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) val <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) val = (chip->image[reg] & ~(mask << shift)) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) change = val != chip->image[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) snd_cs4231_out(chip, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) int mask = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) uinfo->type = mask == 1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) uinfo->value.integer.max = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) int left_reg = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) int right_reg = (kcontrol->private_value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) int shift_left = (kcontrol->private_value >> 16) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) int shift_right = (kcontrol->private_value >> 19) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) int mask = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) int invert = (kcontrol->private_value >> 22) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) (chip->image[left_reg] >> shift_left) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ucontrol->value.integer.value[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) (chip->image[right_reg] >> shift_right) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (invert) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) (mask - ucontrol->value.integer.value[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) ucontrol->value.integer.value[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) (mask - ucontrol->value.integer.value[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) int left_reg = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) int right_reg = (kcontrol->private_value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) int shift_left = (kcontrol->private_value >> 16) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) int shift_right = (kcontrol->private_value >> 19) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) int mask = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) int invert = (kcontrol->private_value >> 22) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) unsigned short val1, val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) val1 = ucontrol->value.integer.value[0] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) val2 = ucontrol->value.integer.value[1] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (invert) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) val1 = mask - val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) val2 = mask - val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) val1 <<= shift_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) val2 <<= shift_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) change = val1 != chip->image[left_reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) change |= val2 != chip->image[right_reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) snd_cs4231_out(chip, left_reg, val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) snd_cs4231_out(chip, right_reg, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .info = snd_cs4231_info_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .private_value = (reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) shift_right, mask, invert) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .info = snd_cs4231_info_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .private_value = (left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static const struct snd_kcontrol_new snd_cs4231_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) 15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .name = "Capture Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .info = snd_cs4231_info_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .get = snd_cs4231_get_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .put = snd_cs4231_put_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /* SPARC specific uses of XCTL{0,1} general purpose outputs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static int snd_cs4231_mixer(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct snd_cs4231 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) int err, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (snd_BUG_ON(!chip || !chip->pcm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) strcpy(card->mixername, chip->pcm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) snd_ctl_new1(&snd_cs4231_controls[idx], chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static int cs4231_attach_begin(struct platform_device *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) struct snd_card **rcard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) struct snd_cs4231 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) *rcard = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) sizeof(struct snd_cs4231), &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) strcpy(card->driver, "CS4231");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) strcpy(card->shortname, "Sun CS4231");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) *rcard = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static int cs4231_attach_finish(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) struct snd_cs4231 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) err = snd_cs4231_pcm(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) err = snd_cs4231_mixer(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) err = snd_cs4231_timer(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) dev_set_drvdata(&chip->op->dev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #ifdef SBUS_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) u32 csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) struct snd_cs4231 *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /*This is IRQ is not raised by the cs4231*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (!(__cs4231_readb(chip, CS4231U(chip, STATUS)) & CS4231_GLOBALIRQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) /* ACK the APC interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) csr = sbus_readl(chip->port + APCCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) sbus_writel(csr, chip->port + APCCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if ((csr & APC_PDMA_READY) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) (csr & APC_PLAY_INT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) (csr & APC_XINT_PNVA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) !(csr & APC_XINT_EMPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) snd_cs4231_play_callback(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if ((csr & APC_CDMA_READY) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) (csr & APC_CAPT_INT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) (csr & APC_XINT_CNVA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) !(csr & APC_XINT_EMPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) snd_cs4231_capture_callback(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (status & CS4231_TIMER_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (chip->timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) snd_timer_interrupt(chip->timer, chip->timer->sticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) snd_cs4231_overrange(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) /* ACK the CS4231 interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) * SBUS DMA routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static int sbus_dma_request(struct cs4231_dma_control *dma_cont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) dma_addr_t bus_addr, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) u32 test, csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) struct sbus_dma_info *base = &dma_cont->sbus_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (len >= (1 << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) spin_lock_irqsave(&base->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) csr = sbus_readl(base->regs + APCCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) test = APC_CDMA_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (base->dir == APC_PLAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) test = APC_PDMA_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) if (!(csr & test))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) test = APC_XINT_CNVA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (base->dir == APC_PLAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) test = APC_XINT_PNVA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (!(csr & test))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) sbus_writel(len, base->regs + base->dir + APCNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) spin_unlock_irqrestore(&base->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) u32 csr, test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) struct sbus_dma_info *base = &dma_cont->sbus_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) spin_lock_irqsave(&base->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) csr = sbus_readl(base->regs + APCCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) APC_XINT_PENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (base->dir == APC_RECORD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) csr |= test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) sbus_writel(csr, base->regs + APCCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) spin_unlock_irqrestore(&base->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) u32 csr, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) struct sbus_dma_info *base = &dma_cont->sbus_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) spin_lock_irqsave(&base->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (!on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) sbus_writel(0, base->regs + base->dir + APCNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) sbus_writel(0, base->regs + base->dir + APCNVA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (base->dir == APC_PLAY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) sbus_writel(0, base->regs + base->dir + APCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) sbus_writel(0, base->regs + base->dir + APCVA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) udelay(1200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) csr = sbus_readl(base->regs + APCCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (base->dir == APC_PLAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) shift = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) csr &= ~(APC_CPAUSE << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) csr |= (APC_CPAUSE << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) sbus_writel(csr, base->regs + APCCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) csr |= (APC_CDMA_READY << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) csr &= ~(APC_CDMA_READY << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) sbus_writel(csr, base->regs + APCCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) spin_unlock_irqrestore(&base->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) struct sbus_dma_info *base = &dma_cont->sbus_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) return sbus_readl(base->regs + base->dir + APCVA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * Init and exit routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static int snd_cs4231_sbus_free(struct snd_cs4231 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) struct platform_device *op = chip->op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (chip->irq[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) free_irq(chip->irq[0], chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (chip->port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) of_iounmap(&op->resource[0], chip->port, chip->regs_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static int snd_cs4231_sbus_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) struct snd_cs4231 *cp = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) return snd_cs4231_sbus_free(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) static const struct snd_device_ops snd_cs4231_sbus_dev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .dev_free = snd_cs4231_sbus_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static int snd_cs4231_sbus_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) struct platform_device *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) struct snd_cs4231 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) spin_lock_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) spin_lock_init(&chip->c_dma.sbus_info.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) spin_lock_init(&chip->p_dma.sbus_info.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) mutex_init(&chip->mce_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) mutex_init(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) chip->op = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) chip->regs_size = resource_size(&op->resource[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) memcpy(&chip->image, &snd_cs4231_original_image,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) sizeof(snd_cs4231_original_image));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) chip->port = of_ioremap(&op->resource[0], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) chip->regs_size, "cs4231");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (!chip->port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) chip->c_dma.sbus_info.regs = chip->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) chip->p_dma.sbus_info.regs = chip->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) chip->c_dma.sbus_info.dir = APC_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) chip->p_dma.sbus_info.dir = APC_PLAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) chip->p_dma.prepare = sbus_dma_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) chip->p_dma.enable = sbus_dma_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) chip->p_dma.request = sbus_dma_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) chip->p_dma.address = sbus_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) chip->c_dma.prepare = sbus_dma_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) chip->c_dma.enable = sbus_dma_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) chip->c_dma.request = sbus_dma_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) chip->c_dma.address = sbus_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (request_irq(op->archdata.irqs[0], snd_cs4231_sbus_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) IRQF_SHARED, "cs4231", chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) dev, op->archdata.irqs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) snd_cs4231_sbus_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) chip->irq[0] = op->archdata.irqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) if (snd_cs4231_probe(chip) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) snd_cs4231_sbus_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) snd_cs4231_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) chip, &snd_cs4231_sbus_dev_ops)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) snd_cs4231_sbus_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) static int cs4231_sbus_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct resource *rp = &op->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) err = cs4231_attach_begin(op, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) card->shortname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) rp->flags & 0xffL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) (unsigned long long)rp->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) op->archdata.irqs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) err = snd_cs4231_sbus_create(card, op, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) return cs4231_attach_finish(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) #ifdef EBUS_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) void *cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) struct snd_cs4231 *chip = cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) snd_cs4231_play_callback(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) int event, void *cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) struct snd_cs4231 *chip = cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) snd_cs4231_capture_callback(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) * EBUS DMA wrappers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) static int _ebus_dma_request(struct cs4231_dma_control *dma_cont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) dma_addr_t bus_addr, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) ebus_dma_enable(&dma_cont->ebus_info, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) ebus_dma_prepare(&dma_cont->ebus_info, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) return ebus_dma_addr(&dma_cont->ebus_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) * Init and exit routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static int snd_cs4231_ebus_free(struct snd_cs4231 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) struct platform_device *op = chip->op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (chip->c_dma.ebus_info.regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) ebus_dma_unregister(&chip->c_dma.ebus_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) of_iounmap(&op->resource[2], chip->c_dma.ebus_info.regs, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (chip->p_dma.ebus_info.regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ebus_dma_unregister(&chip->p_dma.ebus_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) of_iounmap(&op->resource[1], chip->p_dma.ebus_info.regs, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (chip->port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) of_iounmap(&op->resource[0], chip->port, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) static int snd_cs4231_ebus_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) struct snd_cs4231 *cp = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) return snd_cs4231_ebus_free(cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) static const struct snd_device_ops snd_cs4231_ebus_dev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .dev_free = snd_cs4231_ebus_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) static int snd_cs4231_ebus_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) struct platform_device *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) struct snd_cs4231 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) spin_lock_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) spin_lock_init(&chip->c_dma.ebus_info.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) spin_lock_init(&chip->p_dma.ebus_info.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) mutex_init(&chip->mce_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) mutex_init(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) chip->flags |= CS4231_FLAG_EBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) chip->op = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) memcpy(&chip->image, &snd_cs4231_original_image,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) sizeof(snd_cs4231_original_image));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) chip->c_dma.ebus_info.client_cookie = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) chip->c_dma.ebus_info.irq = op->archdata.irqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) strcpy(chip->p_dma.ebus_info.name, "cs4231(play)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) chip->p_dma.ebus_info.client_cookie = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) chip->p_dma.ebus_info.irq = op->archdata.irqs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) chip->p_dma.prepare = _ebus_dma_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) chip->p_dma.enable = _ebus_dma_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) chip->p_dma.request = _ebus_dma_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) chip->p_dma.address = _ebus_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) chip->c_dma.prepare = _ebus_dma_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) chip->c_dma.enable = _ebus_dma_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) chip->c_dma.request = _ebus_dma_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) chip->c_dma.address = _ebus_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) chip->port = of_ioremap(&op->resource[0], 0, 0x10, "cs4231");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) chip->p_dma.ebus_info.regs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) of_ioremap(&op->resource[1], 0, 0x10, "cs4231_pdma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) chip->c_dma.ebus_info.regs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) of_ioremap(&op->resource[2], 0, 0x10, "cs4231_cdma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) if (!chip->port || !chip->p_dma.ebus_info.regs ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) !chip->c_dma.ebus_info.regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) snd_cs4231_ebus_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) if (ebus_dma_register(&chip->c_dma.ebus_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) snd_cs4231_ebus_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) snd_cs4231_ebus_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) if (ebus_dma_register(&chip->p_dma.ebus_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) snd_cs4231_ebus_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) snd_cs4231_ebus_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (snd_cs4231_probe(chip) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) snd_cs4231_ebus_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) snd_cs4231_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) chip, &snd_cs4231_ebus_dev_ops)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) snd_cs4231_ebus_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static int cs4231_ebus_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) err = cs4231_attach_begin(op, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) sprintf(card->longname, "%s at 0x%llx, irq %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) card->shortname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) op->resource[0].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) op->archdata.irqs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) err = snd_cs4231_ebus_create(card, op, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) return cs4231_attach_finish(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) static int cs4231_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) #ifdef EBUS_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) if (of_node_name_eq(op->dev.of_node->parent, "ebus"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) return cs4231_ebus_probe(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) #ifdef SBUS_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) if (of_node_name_eq(op->dev.of_node->parent, "sbus") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) of_node_name_eq(op->dev.of_node->parent, "sbi"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) return cs4231_sbus_probe(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) static int cs4231_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) struct snd_cs4231 *chip = dev_get_drvdata(&op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) snd_card_free(chip->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) static const struct of_device_id cs4231_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .name = "SUNW,CS4231",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .name = "audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .compatible = "SUNW,CS4231",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) MODULE_DEVICE_TABLE(of, cs4231_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) static struct platform_driver cs4231_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .name = "audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .of_match_table = cs4231_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .probe = cs4231_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .remove = cs4231_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) module_platform_driver(cs4231_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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