^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for AMD7930 sound chips found on Sparcs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based entirely upon drivers/sbus/audio/amd7930.c which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1996,1997 Thomas K. Dyas (tdyas@eden.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * --- Notes from Thomas's original driver ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This is the lowlevel driver for the AMD7930 audio chip found on all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * sun4c machines and some sun4m machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The amd7930 is actually an ISDN chip which has a very simple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * integrated audio encoder/decoder. When Sun decided on what chip to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * use for audio, they had the brilliant idea of using the amd7930 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * only connecting the audio encoder/decoder pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Thanks to the AMD engineer who was able to get us the AMD79C30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * databook which has all the programming information and gain tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Advanced Micro Devices' Am79C30A is an ISDN/audio chip used in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * SparcStation 1+. The chip provides microphone and speaker interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * which provide mono-channel audio at 8K samples per second via either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * 8-bit A-law or 8-bit mu-law encoding. Also, the chip features an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * ISDN BRI Line Interface Unit (LIU), I.430 S/T physical interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * which performs basic D channel LAPD processing and provides raw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * B channel data. The digital audio channel, the two ISDN B channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * and two 64 Kbps channels to the microprocessor are all interconnected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * via a multiplexer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * --- End of notes from Thoamas's original driver ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_PARM_DESC(index, "Index value for Sun AMD7930 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_PARM_DESC(id, "ID string for Sun AMD7930 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_PARM_DESC(enable, "Enable Sun AMD7930 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MODULE_AUTHOR("Thomas K. Dyas and David S. Miller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MODULE_DESCRIPTION("Sun AMD7930");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MODULE_SUPPORTED_DEVICE("{{Sun,AMD7930}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Device register layout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Register interface presented to the CPU by the amd7930. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AMD7930_CR 0x00UL /* Command Register (W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AMD7930_IR AMD7930_CR /* Interrupt Register (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AMD7930_DR 0x01UL /* Data Register (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AMD7930_DSR1 0x02UL /* D-channel Status Register 1 (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AMD7930_DER 0x03UL /* D-channel Error Register (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AMD7930_DCTB 0x04UL /* D-channel Transmit Buffer (W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AMD7930_DCRB AMD7930_DCTB /* D-channel Receive Buffer (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AMD7930_BBTB 0x05UL /* Bb-channel Transmit Buffer (W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AMD7930_BBRB AMD7930_BBTB /* Bb-channel Receive Buffer (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AMD7930_BCTB 0x06UL /* Bc-channel Transmit Buffer (W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AMD7930_BCRB AMD7930_BCTB /* Bc-channel Receive Buffer (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AMD7930_DSR2 0x07UL /* D-channel Status Register 2 (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Indirect registers in the Main Audio Processor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct amd7930_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __u16 x[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __u16 r[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __u16 gx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __u16 gr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __u16 ger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __u16 stgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __u16 ftgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __u16 atgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __u8 mmr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __u8 mmr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* After an amd7930 interrupt, reading the Interrupt Register (ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * clears the interrupt and returns a bitmask indicating which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * interrupt source(s) require service.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AMR_IR_DTTHRSH 0x01 /* D-channel xmit threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AMR_IR_DRTHRSH 0x02 /* D-channel recv threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AMR_IR_DSRI 0x04 /* D-channel packet status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AMR_IR_DERI 0x08 /* D-channel error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AMR_IR_BBUF 0x10 /* B-channel data xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AMR_IR_LSRI 0x20 /* LIU status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AMR_IR_DSR2I 0x40 /* D-channel buffer status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AMR_IR_MLTFRMI 0x80 /* multiframe or PP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* The amd7930 has "indirect registers" which are accessed by writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * the register number into the Command Register and then reading or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * writing values from the Data Register as appropriate. We define the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * AMR_* macros to be the indirect register numbers and AM_* macros to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * be bits in whatever register is referred to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AMR_INIT 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AM_INIT_ACTIVE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AM_INIT_DATAONLY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AM_INIT_POWERDOWN 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AM_INIT_DISABLE_INTS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AMR_INIT2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AM_INIT2_ENABLE_POWERDOWN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AM_INIT2_ENABLE_MULTIFRAME 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Line Interface Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AMR_LIU_LSR 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AM_LIU_LSR_STATE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AM_LIU_LSR_F3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AM_LIU_LSR_F7 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AM_LIU_LSR_F8 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AM_LIU_LSR_HSW 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AM_LIU_LSR_HSW_CHG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AMR_LIU_LPR 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AMR_LIU_LMR1 0xA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AM_LIU_LMR1_B1_ENABL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AM_LIU_LMR1_B2_ENABL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AM_LIU_LMR1_F_DISABL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AM_LIU_LMR1_FA_DISABL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AM_LIU_LMR1_REQ_ACTIV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AM_LIU_LMR1_F8_F3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AM_LIU_LMR1_LIU_ENABL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AMR_LIU_LMR2 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AM_LIU_LMR2_DECHO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AM_LIU_LMR2_DLOOP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AM_LIU_LMR2_DBACKOFF 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AM_LIU_LMR2_EN_F3_INT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AM_LIU_LMR2_EN_F8_INT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AM_LIU_LMR2_EN_HSW_INT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AM_LIU_LMR2_EN_F7_INT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AMR_LIU_2_4 0xA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AMR_LIU_MF 0xA6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AMR_LIU_MFSB 0xA7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AMR_LIU_MFQB 0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Multiplexor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AMR_MUX_MCR1 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AMR_MUX_MCR2 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AMR_MUX_MCR3 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AM_MUX_CHANNEL_B1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define AM_MUX_CHANNEL_B2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AM_MUX_CHANNEL_Ba 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AM_MUX_CHANNEL_Bb 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AM_MUX_CHANNEL_Bc 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define AM_MUX_CHANNEL_Bd 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AM_MUX_CHANNEL_Be 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AM_MUX_CHANNEL_Bf 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AMR_MUX_MCR4 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define AM_MUX_MCR4_ENABLE_INTS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AM_MUX_MCR4_REVERSE_Bb 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define AM_MUX_MCR4_REVERSE_Bc 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AMR_MUX_1_4 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Main Audio Processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AMR_MAP_X 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AMR_MAP_R 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define AMR_MAP_GX 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AMR_MAP_GR 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AMR_MAP_GER 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AMR_MAP_STGR 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AMR_MAP_FTGR_1_2 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define AMR_MAP_ATGR_1_2 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AMR_MAP_MMR1 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AM_MAP_MMR1_ALAW 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AM_MAP_MMR1_GX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AM_MAP_MMR1_GR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AM_MAP_MMR1_GER 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AM_MAP_MMR1_X 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AM_MAP_MMR1_R 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AM_MAP_MMR1_STG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AM_MAP_MMR1_LOOPBACK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AMR_MAP_MMR2 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AM_MAP_MMR2_AINB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define AM_MAP_MMR2_LS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AM_MAP_MMR2_ENABLE_DTMF 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define AM_MAP_MMR2_ENABLE_TONEGEN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AM_MAP_MMR2_ENABLE_TONERING 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AM_MAP_MMR2_DISABLE_HIGHPASS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AM_MAP_MMR2_DISABLE_AUTOZERO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define AMR_MAP_1_10 0x6B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AMR_MAP_MMR3 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AMR_MAP_STRA 0x6D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AMR_MAP_STRF 0x6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AMR_MAP_PEAKX 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AMR_MAP_PEAKR 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AMR_MAP_15_16 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Data Link Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AMR_DLC_FRAR_1_2_3 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AMR_DLC_SRAR_1_2_3 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AMR_DLC_TAR 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AMR_DLC_DRLR 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AMR_DLC_DTCR 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AMR_DLC_DMR1 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AMR_DLC_DMR1_DTTHRSH_INT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AMR_DLC_DMR1_DRTHRSH_INT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define AMR_DLC_DMR1_TAR_ENABL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AMR_DLC_DMR1_EORP_INT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define AMR_DLC_DMR1_EN_ADDR1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define AMR_DLC_DMR1_EN_ADDR2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AMR_DLC_DMR1_EN_ADDR3 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AMR_DLC_DMR1_EN_ADDR4 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define AMR_DLC_DMR1_EN_ADDRS 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define AMR_DLC_DMR2 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AMR_DLC_DMR2_RABRT_INT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define AMR_DLC_DMR2_RESID_INT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AMR_DLC_DMR2_COLL_INT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AMR_DLC_DMR2_FCS_INT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define AMR_DLC_DMR2_OVFL_INT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define AMR_DLC_DMR2_UNFL_INT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AMR_DLC_DMR2_OVRN_INT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AMR_DLC_DMR2_UNRN_INT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define AMR_DLC_1_7 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define AMR_DLC_DRCR 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define AMR_DLC_RNGR1 0x8A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define AMR_DLC_RNGR2 0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define AMR_DLC_FRAR4 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define AMR_DLC_SRAR4 0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define AMR_DLC_DMR3 0x8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define AMR_DLC_DMR3_VA_INT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define AMR_DLC_DMR3_EOTP_INT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AMR_DLC_DMR3_LBRP_INT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define AMR_DLC_DMR3_RBA_INT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define AMR_DLC_DMR3_LBT_INT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define AMR_DLC_DMR3_TBE_INT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define AMR_DLC_DMR3_RPLOST_INT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define AMR_DLC_DMR3_KEEP_FCS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define AMR_DLC_DMR4 0x8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define AMR_DLC_DMR4_RCV_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define AMR_DLC_DMR4_RCV_2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define AMR_DLC_DMR4_RCV_4 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define AMR_DLC_DMR4_RCV_8 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define AMR_DLC_DMR4_RCV_16 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define AMR_DLC_DMR4_RCV_24 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define AMR_DLC_DMR4_RCV_30 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define AMR_DLC_DMR4_XMT_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define AMR_DLC_DMR4_XMT_2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define AMR_DLC_DMR4_XMT_4 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define AMR_DLC_DMR4_XMT_8 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define AMR_DLC_DMR4_XMT_10 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define AMR_DLC_DMR4_XMT_14 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define AMR_DLC_DMR4_IDLE_MARK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define AMR_DLC_DMR4_IDLE_FLAG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define AMR_DLC_DMR4_ADDR_BOTH 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define AMR_DLC_DMR4_ADDR_1ST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define AMR_DLC_DMR4_ADDR_2ND 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define AMR_DLC_DMR4_CR_ENABLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define AMR_DLC_12_15 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define AMR_DLC_ASR 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define AMR_DLC_EFCR 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define AMR_DLC_EFCR_EXTEND_FIFO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define AMR_DLC_EFCR_SEC_PKT_INT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define AMR_DSR1_VADDR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define AMR_DSR1_EORP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define AMR_DSR1_PKT_IP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define AMR_DSR1_DECHO_ON 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define AMR_DSR1_DLOOP_ON 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define AMR_DSR1_DBACK_OFF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define AMR_DSR1_EOTP 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define AMR_DSR1_CXMT_ABRT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define AMR_DSR2_LBRP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define AMR_DSR2_RBA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define AMR_DSR2_RPLOST 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define AMR_DSR2_LAST_BYTE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define AMR_DSR2_TBE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define AMR_DSR2_MARK_IDLE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define AMR_DSR2_FLAG_IDLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define AMR_DSR2_SECOND_PKT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define AMR_DER_RABRT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define AMR_DER_RFRAME 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define AMR_DER_COLLISION 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define AMR_DER_FCS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define AMR_DER_OVFL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define AMR_DER_UNFL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define AMR_DER_OVRN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define AMR_DER_UNRN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Peripheral Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define AMR_PP_PPCR1 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define AMR_PP_PPSR 0xC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define AMR_PP_PPIER 0xC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define AMR_PP_MTDR 0xC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define AMR_PP_MRDR 0xC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define AMR_PP_CITDR0 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define AMR_PP_CIRDR0 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define AMR_PP_CITDR1 0xC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define AMR_PP_CIRDR1 0xC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define AMR_PP_PPCR2 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define AMR_PP_PPCR3 0xC9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct snd_amd7930 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define AMD7930_FLAG_PLAYBACK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define AMD7930_FLAG_CAPTURE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct amd7930_map map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct snd_pcm_substream *playback_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct snd_pcm_substream *capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Playback/Capture buffer state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned char *p_orig, *p_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int p_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned char *c_orig, *c_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int c_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int rgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int pgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int mgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct platform_device *op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct snd_amd7930 *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static struct snd_amd7930 *amd7930_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Idle the AMD7930 chip. The amd->lock is not held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static __inline__ void amd7930_idle(struct snd_amd7930 *amd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) spin_lock_irqsave(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) sbus_writeb(0, amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spin_unlock_irqrestore(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Enable chip interrupts. The amd->lock is not held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static __inline__ void amd7930_enable_ints(struct snd_amd7930 *amd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) spin_lock_irqsave(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) sbus_writeb(AM_INIT_ACTIVE, amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) spin_unlock_irqrestore(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Disable chip interrupts. The amd->lock is not held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static __inline__ void amd7930_disable_ints(struct snd_amd7930 *amd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) spin_lock_irqsave(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) sbus_writeb(AM_INIT_ACTIVE | AM_INIT_DISABLE_INTS, amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) spin_unlock_irqrestore(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Commit amd7930_map settings to the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * The amd->lock is held and local interrupts are disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void __amd7930_write_map(struct snd_amd7930 *amd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct amd7930_map *map = &amd->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) sbus_writeb(AMR_MAP_GX, amd->regs + AMD7930_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) sbus_writeb(((map->gx >> 0) & 0xff), amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) sbus_writeb(((map->gx >> 8) & 0xff), amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) sbus_writeb(AMR_MAP_GR, amd->regs + AMD7930_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) sbus_writeb(((map->gr >> 0) & 0xff), amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) sbus_writeb(((map->gr >> 8) & 0xff), amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) sbus_writeb(AMR_MAP_STGR, amd->regs + AMD7930_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) sbus_writeb(((map->stgr >> 0) & 0xff), amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) sbus_writeb(((map->stgr >> 8) & 0xff), amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) sbus_writeb(AMR_MAP_GER, amd->regs + AMD7930_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) sbus_writeb(((map->ger >> 0) & 0xff), amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) sbus_writeb(((map->ger >> 8) & 0xff), amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) sbus_writeb(AMR_MAP_MMR1, amd->regs + AMD7930_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) sbus_writeb(map->mmr1, amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) sbus_writeb(AMR_MAP_MMR2, amd->regs + AMD7930_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) sbus_writeb(map->mmr2, amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* gx, gr & stg gains. this table must contain 256 elements with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * the 0th being "infinity" (the magic value 9008). The remaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * elements match sun's gain curve (but with higher resolution):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * -18 to 0dB in .16dB steps then 0 to 12dB in .08dB steps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static __const__ __u16 gx_coeff[256] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 0x9008, 0x8b7c, 0x8b51, 0x8b45, 0x8b42, 0x8b3b, 0x8b36, 0x8b33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0x8b32, 0x8b2a, 0x8b2b, 0x8b2c, 0x8b25, 0x8b23, 0x8b22, 0x8b22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 0x9122, 0x8b1a, 0x8aa3, 0x8aa3, 0x8b1c, 0x8aa6, 0x912d, 0x912b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0x8aab, 0x8b12, 0x8aaa, 0x8ab2, 0x9132, 0x8ab4, 0x913c, 0x8abb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0x9142, 0x9144, 0x9151, 0x8ad5, 0x8aeb, 0x8a79, 0x8a5a, 0x8a4a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 0x8b03, 0x91c2, 0x91bb, 0x8a3f, 0x8a33, 0x91b2, 0x9212, 0x9213,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 0x8a2c, 0x921d, 0x8a23, 0x921a, 0x9222, 0x9223, 0x922d, 0x9231,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 0x9234, 0x9242, 0x925b, 0x92dd, 0x92c1, 0x92b3, 0x92ab, 0x92a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 0x92a2, 0x932b, 0x9341, 0x93d3, 0x93b2, 0x93a2, 0x943c, 0x94b2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 0x953a, 0x9653, 0x9782, 0x9e21, 0x9d23, 0x9cd2, 0x9c23, 0x9baa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 0x9bde, 0x9b33, 0x9b22, 0x9b1d, 0x9ab2, 0xa142, 0xa1e5, 0x9a3b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 0xa213, 0xa1a2, 0xa231, 0xa2eb, 0xa313, 0xa334, 0xa421, 0xa54b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 0xada4, 0xac23, 0xab3b, 0xaaab, 0xaa5c, 0xb1a3, 0xb2ca, 0xb3bd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0xbe24, 0xbb2b, 0xba33, 0xc32b, 0xcb5a, 0xd2a2, 0xe31d, 0x0808,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 0x72ba, 0x62c2, 0x5c32, 0x52db, 0x513e, 0x4cce, 0x43b2, 0x4243,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x41b4, 0x3b12, 0x3bc3, 0x3df2, 0x34bd, 0x3334, 0x32c2, 0x3224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 0x31aa, 0x2a7b, 0x2aaa, 0x2b23, 0x2bba, 0x2c42, 0x2e23, 0x25bb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 0x242b, 0x240f, 0x231a, 0x22bb, 0x2241, 0x2223, 0x221f, 0x1a33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 0x1a4a, 0x1acd, 0x2132, 0x1b1b, 0x1b2c, 0x1b62, 0x1c12, 0x1c32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0x1d1b, 0x1e71, 0x16b1, 0x1522, 0x1434, 0x1412, 0x1352, 0x1323,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 0x1315, 0x12bc, 0x127a, 0x1235, 0x1226, 0x11a2, 0x1216, 0x0a2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 0x11bc, 0x11d1, 0x1163, 0x0ac2, 0x0ab2, 0x0aab, 0x0b1b, 0x0b23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 0x0b33, 0x0c0f, 0x0bb3, 0x0c1b, 0x0c3e, 0x0cb1, 0x0d4c, 0x0ec1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 0x079a, 0x0614, 0x0521, 0x047c, 0x0422, 0x03b1, 0x03e3, 0x0333,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 0x0322, 0x031c, 0x02aa, 0x02ba, 0x02f2, 0x0242, 0x0232, 0x0227,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 0x0222, 0x021b, 0x01ad, 0x0212, 0x01b2, 0x01bb, 0x01cb, 0x01f6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 0x0152, 0x013a, 0x0133, 0x0131, 0x012c, 0x0123, 0x0122, 0x00a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 0x011b, 0x011e, 0x0114, 0x00b1, 0x00aa, 0x00b3, 0x00bd, 0x00ba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 0x00c5, 0x00d3, 0x00f3, 0x0062, 0x0051, 0x0042, 0x003b, 0x0033,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 0x0032, 0x002a, 0x002c, 0x0025, 0x0023, 0x0022, 0x001a, 0x0021,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 0x001b, 0x001b, 0x001d, 0x0015, 0x0013, 0x0013, 0x0012, 0x0012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 0x000a, 0x000a, 0x0011, 0x0011, 0x000b, 0x000b, 0x000c, 0x000e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static __const__ __u16 ger_coeff[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 0x431f, /* 5. dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 0x331f, /* 5.5 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 0x40dd, /* 6. dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 0x11dd, /* 6.5 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 0x440f, /* 7. dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 0x411f, /* 7.5 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 0x311f, /* 8. dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 0x5520, /* 8.5 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 0x10dd, /* 9. dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 0x4211, /* 9.5 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 0x410f, /* 10. dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 0x111f, /* 10.5 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 0x600b, /* 11. dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 0x00dd, /* 11.5 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 0x4210, /* 12. dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 0x110f, /* 13. dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 0x7200, /* 14. dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 0x2110, /* 15. dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 0x2200, /* 15.9 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 0x000b, /* 16.9 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 0x000f /* 18. dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Update amd7930_map settings and program them into the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * The amd->lock is held and local interrupts are disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static void __amd7930_update_map(struct snd_amd7930 *amd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct amd7930_map *map = &amd->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) map->gx = gx_coeff[amd->rgain];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) map->stgr = gx_coeff[amd->mgain];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) level = (amd->pgain * (256 + ARRAY_SIZE(ger_coeff))) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (level >= 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) map->ger = ger_coeff[level - 256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) map->gr = gx_coeff[255];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) map->ger = ger_coeff[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) map->gr = gx_coeff[level];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) __amd7930_write_map(amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static irqreturn_t snd_amd7930_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct snd_amd7930 *amd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned int elapsed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u8 ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) spin_lock(&amd->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) elapsed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ir = sbus_readb(amd->regs + AMD7930_IR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ir & AMR_IR_BBUF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (amd->flags & AMD7930_FLAG_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (amd->p_left > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) byte = *(amd->p_cur++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) amd->p_left--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) sbus_writeb(byte, amd->regs + AMD7930_BBTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (amd->p_left == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) elapsed |= AMD7930_FLAG_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) sbus_writeb(0, amd->regs + AMD7930_BBTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) } else if (amd->flags & AMD7930_FLAG_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) byte = sbus_readb(amd->regs + AMD7930_BBRB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (amd->c_left > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) *(amd->c_cur++) = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) amd->c_left--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (amd->c_left == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) elapsed |= AMD7930_FLAG_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) spin_unlock(&amd->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (elapsed & AMD7930_FLAG_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) snd_pcm_period_elapsed(amd->playback_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) snd_pcm_period_elapsed(amd->capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int snd_amd7930_trigger(struct snd_amd7930 *amd, unsigned int flag, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) spin_lock_irqsave(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (cmd == SNDRV_PCM_TRIGGER_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!(amd->flags & flag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) amd->flags |= flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* Enable B channel interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) sbus_writeb(AM_MUX_MCR4_ENABLE_INTS, amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (amd->flags & flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) amd->flags &= ~flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Disable B channel interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) sbus_writeb(0, amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) spin_unlock_irqrestore(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int snd_amd7930_playback_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return snd_amd7930_trigger(amd, AMD7930_FLAG_PLAYBACK, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int snd_amd7930_capture_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return snd_amd7930_trigger(amd, AMD7930_FLAG_CAPTURE, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int snd_amd7930_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) unsigned int size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u8 new_mmr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) spin_lock_irqsave(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) amd->flags |= AMD7930_FLAG_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Setup the pseudo-dma transfer pointers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) amd->p_orig = amd->p_cur = runtime->dma_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) amd->p_left = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Put the chip into the correct encoding format. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) new_mmr1 = amd->map.mmr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) new_mmr1 |= AM_MAP_MMR1_ALAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) new_mmr1 &= ~AM_MAP_MMR1_ALAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (new_mmr1 != amd->map.mmr1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) amd->map.mmr1 = new_mmr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) __amd7930_update_map(amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) spin_unlock_irqrestore(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int snd_amd7930_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned int size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u8 new_mmr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) spin_lock_irqsave(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) amd->flags |= AMD7930_FLAG_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* Setup the pseudo-dma transfer pointers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) amd->c_orig = amd->c_cur = runtime->dma_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) amd->c_left = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* Put the chip into the correct encoding format. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) new_mmr1 = amd->map.mmr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) new_mmr1 |= AM_MAP_MMR1_ALAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) new_mmr1 &= ~AM_MAP_MMR1_ALAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (new_mmr1 != amd->map.mmr1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) amd->map.mmr1 = new_mmr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) __amd7930_update_map(amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) spin_unlock_irqrestore(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static snd_pcm_uframes_t snd_amd7930_playback_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (!(amd->flags & AMD7930_FLAG_PLAYBACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ptr = amd->p_cur - amd->p_orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static snd_pcm_uframes_t snd_amd7930_capture_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (!(amd->flags & AMD7930_FLAG_CAPTURE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ptr = amd->c_cur - amd->c_orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Playback and capture have identical properties. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static const struct snd_pcm_hardware snd_amd7930_pcm_hw =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) SNDRV_PCM_INFO_HALF_DUPLEX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .rates = SNDRV_PCM_RATE_8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .rate_max = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .buffer_bytes_max = (64*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .period_bytes_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .period_bytes_max = (64*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static int snd_amd7930_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) amd->playback_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) runtime->hw = snd_amd7930_pcm_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static int snd_amd7930_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) amd->capture_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) runtime->hw = snd_amd7930_pcm_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int snd_amd7930_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) amd->playback_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static int snd_amd7930_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) amd->capture_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static const struct snd_pcm_ops snd_amd7930_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .open = snd_amd7930_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .close = snd_amd7930_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .prepare = snd_amd7930_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .trigger = snd_amd7930_playback_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .pointer = snd_amd7930_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const struct snd_pcm_ops snd_amd7930_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .open = snd_amd7930_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .close = snd_amd7930_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .prepare = snd_amd7930_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .trigger = snd_amd7930_capture_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .pointer = snd_amd7930_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static int snd_amd7930_pcm(struct snd_amd7930 *amd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if ((err = snd_pcm_new(amd->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* ID */ "sun_amd7930",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* device */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* playback count */ 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* capture count */ 1, &pcm)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_amd7930_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_amd7930_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pcm->private_data = amd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) strcpy(pcm->name, amd->card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) amd->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) NULL, 64*1024, 64*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define VOLUME_MONITOR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define VOLUME_CAPTURE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define VOLUME_PLAYBACK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static int snd_amd7930_info_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) uinfo->value.integer.max = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int snd_amd7930_get_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct snd_amd7930 *amd = snd_kcontrol_chip(kctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int type = kctl->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int *swval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case VOLUME_MONITOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) swval = &amd->mgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) case VOLUME_CAPTURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) swval = &amd->rgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) case VOLUME_PLAYBACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) swval = &amd->pgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ucontrol->value.integer.value[0] = *swval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static int snd_amd7930_put_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct snd_amd7930 *amd = snd_kcontrol_chip(kctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int type = kctl->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) int *swval, change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case VOLUME_MONITOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) swval = &amd->mgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case VOLUME_CAPTURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) swval = &amd->rgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) case VOLUME_PLAYBACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) swval = &amd->pgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) spin_lock_irqsave(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (*swval != ucontrol->value.integer.value[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) *swval = ucontrol->value.integer.value[0] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) __amd7930_update_map(amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) spin_unlock_irqrestore(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static const struct snd_kcontrol_new amd7930_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .name = "Monitor Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .info = snd_amd7930_info_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .get = snd_amd7930_get_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .put = snd_amd7930_put_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .private_value = VOLUME_MONITOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .name = "Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .info = snd_amd7930_info_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .get = snd_amd7930_get_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .put = snd_amd7930_put_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .private_value = VOLUME_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .name = "Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .info = snd_amd7930_info_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .get = snd_amd7930_get_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .put = snd_amd7930_put_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .private_value = VOLUME_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static int snd_amd7930_mixer(struct snd_amd7930 *amd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) int idx, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (snd_BUG_ON(!amd || !amd->card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) card = amd->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) strcpy(card->mixername, card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) for (idx = 0; idx < ARRAY_SIZE(amd7930_controls); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if ((err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) snd_ctl_new1(&amd7930_controls[idx], amd))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int snd_amd7930_free(struct snd_amd7930 *amd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct platform_device *op = amd->op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) amd7930_idle(amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (amd->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) free_irq(amd->irq, amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (amd->regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) of_iounmap(&op->resource[0], amd->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) resource_size(&op->resource[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) kfree(amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int snd_amd7930_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct snd_amd7930 *amd = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return snd_amd7930_free(amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const struct snd_device_ops snd_amd7930_dev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .dev_free = snd_amd7930_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static int snd_amd7930_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct platform_device *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int irq, int dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct snd_amd7930 **ramd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct snd_amd7930 *amd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) *ramd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) amd = kzalloc(sizeof(*amd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (amd == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) spin_lock_init(&amd->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) amd->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) amd->op = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) amd->regs = of_ioremap(&op->resource[0], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) resource_size(&op->resource[0]), "amd7930");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (!amd->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) snd_printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) "amd7930-%d: Unable to map chip registers.\n", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) kfree(amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) amd7930_idle(amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (request_irq(irq, snd_amd7930_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) IRQF_SHARED, "amd7930", amd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) snd_printk(KERN_ERR "amd7930-%d: Unable to grab IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dev, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) snd_amd7930_free(amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) amd->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) amd7930_enable_ints(amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) spin_lock_irqsave(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) amd->rgain = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) amd->pgain = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) amd->mgain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) memset(&amd->map, 0, sizeof(amd->map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) amd->map.mmr1 = (AM_MAP_MMR1_GX | AM_MAP_MMR1_GER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) AM_MAP_MMR1_GR | AM_MAP_MMR1_STG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) amd->map.mmr2 = (AM_MAP_MMR2_LS | AM_MAP_MMR2_AINB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) __amd7930_update_map(amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* Always MUX audio (Ba) to channel Bb. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) sbus_writeb(AMR_MUX_MCR1, amd->regs + AMD7930_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) sbus_writeb(AM_MUX_CHANNEL_Ba | (AM_MUX_CHANNEL_Bb << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) amd->regs + AMD7930_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) spin_unlock_irqrestore(&amd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) amd, &snd_amd7930_dev_ops)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) snd_amd7930_free(amd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) *ramd = amd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static int amd7930_sbus_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct resource *rp = &op->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static int dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct snd_amd7930 *amd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) int err, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) irq = op->archdata.irqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (dev_num >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (!enable[dev_num]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) dev_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) err = snd_card_new(&op->dev, index[dev_num], id[dev_num],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) THIS_MODULE, 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) strcpy(card->driver, "AMD7930");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) strcpy(card->shortname, "Sun AMD7930");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) sprintf(card->longname, "%s at 0x%02lx:0x%08Lx, irq %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) card->shortname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) rp->flags & 0xffL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) (unsigned long long)rp->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if ((err = snd_amd7930_create(card, op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) irq, dev_num, &amd)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if ((err = snd_amd7930_pcm(amd)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if ((err = snd_amd7930_mixer(amd)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if ((err = snd_card_register(card)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) amd->next = amd7930_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) amd7930_list = amd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dev_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static const struct of_device_id amd7930_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .name = "audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) MODULE_DEVICE_TABLE(of, amd7930_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static struct platform_driver amd7930_sbus_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .name = "audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .of_match_table = amd7930_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .probe = amd7930_sbus_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int __init amd7930_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return platform_driver_register(&amd7930_sbus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static void __exit amd7930_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct snd_amd7930 *p = amd7930_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) while (p != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct snd_amd7930 *next = p->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) snd_card_free(p->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) p = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) amd7930_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) platform_driver_unregister(&amd7930_sbus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) module_init(amd7930_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) module_exit(amd7930_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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