^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xtfpga I2S controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Cadence Design Systems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DRV_NAME "xtfpga-i2s"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define XTFPGA_I2S_VERSION 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define XTFPGA_I2S_CONFIG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define XTFPGA_I2S_INT_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define XTFPGA_I2S_INT_STATUS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define XTFPGA_I2S_CHAN0_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define XTFPGA_I2S_CHAN1_DATA 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define XTFPGA_I2S_CHAN2_DATA 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define XTFPGA_I2S_CHAN3_DATA 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define XTFPGA_I2S_CONFIG_TX_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XTFPGA_I2S_CONFIG_INT_ENABLE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XTFPGA_I2S_CONFIG_LEFT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define XTFPGA_I2S_CONFIG_RATIO_BASE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XTFPGA_I2S_CONFIG_RATIO_MASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XTFPGA_I2S_CONFIG_RES_BASE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define XTFPGA_I2S_CONFIG_RES_MASK 0x003f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define XTFPGA_I2S_CONFIG_LEVEL_BASE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define XTFPGA_I2S_CONFIG_LEVEL_MASK 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XTFPGA_I2S_CONFIG_CHANNEL_BASE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define XTFPGA_I2S_INT_UNDERRUN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XTFPGA_I2S_INT_LEVEL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XTFPGA_I2S_INT_VALID 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define XTFPGA_I2S_FIFO_SIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * I2S controller operation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Enabling TX: output 1 period of zeros (starting with left channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * and then queued data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Level status and interrupt: whenever FIFO level is below FIFO trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * level status is 1 and an IRQ is asserted (if enabled).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Underrun status and interrupt: whenever FIFO is empty, underrun status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * is 1 and an IRQ is asserted (if enabled).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct xtfpga_i2s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* current playback substream. NULL if not playing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Access to that field is synchronized between the interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * and userspace through RCU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Interrupt handler (threaded part) does PIO on substream data in RCU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * read-side critical section. Trigger callback sets and clears the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * pointer when the playback is started and stopped with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * rcu_assign_pointer. When userspace is about to free the playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * stream in the pcm_close callback it synchronizes with the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * handler by means of synchronize_rcu call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct snd_pcm_substream __rcu *tx_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned (*tx_fn)(struct xtfpga_i2s *i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct snd_pcm_runtime *runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned tx_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned tx_ptr; /* next frame index in the sample buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* current fifo level estimate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Doesn't have to be perfectly accurate, but must be not less than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * the actual FIFO level in order to avoid stall on push attempt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned tx_fifo_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* FIFO level at which level interrupt occurs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned tx_fifo_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* maximal FIFO level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned tx_fifo_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static bool xtfpga_i2s_wr_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return reg >= XTFPGA_I2S_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static bool xtfpga_i2s_rd_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return reg < XTFPGA_I2S_CHAN0_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static bool xtfpga_i2s_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return reg == XTFPGA_I2S_INT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct regmap_config xtfpga_i2s_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .max_register = XTFPGA_I2S_CHAN3_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .writeable_reg = xtfpga_i2s_wr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .readable_reg = xtfpga_i2s_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .volatile_reg = xtfpga_i2s_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Generate functions that do PIO from TX DMA area to FIFO for all supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * stream formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Functions will be called xtfpga_pcm_tx_<channels>x<sample bits>, e.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * xtfpga_pcm_tx_2x16 for 16-bit stereo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * FIFO consists of 32-bit words, one word per channel, always 2 channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * If I2S interface is configured with smaller sample resolution, only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * the LSB of each word is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define xtfpga_pcm_tx_fn(channels, sample_bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static unsigned xtfpga_pcm_tx_##channels##x##sample_bits( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct xtfpga_i2s *i2s, struct snd_pcm_runtime *runtime, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned tx_ptr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const u##sample_bits (*p)[channels] = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) (void *)runtime->dma_area; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) for (; i2s->tx_fifo_level < i2s->tx_fifo_high; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) i2s->tx_fifo_level += 2) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) iowrite32(p[tx_ptr][0], \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) iowrite32(p[tx_ptr][channels - 1], \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (++tx_ptr >= runtime->buffer_size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) tx_ptr = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return tx_ptr; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) xtfpga_pcm_tx_fn(1, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) xtfpga_pcm_tx_fn(2, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) xtfpga_pcm_tx_fn(1, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) xtfpga_pcm_tx_fn(2, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #undef xtfpga_pcm_tx_fn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static bool xtfpga_pcm_push_tx(struct xtfpga_i2s *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct snd_pcm_substream *tx_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) bool tx_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tx_substream = rcu_dereference(i2s->tx_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tx_active = tx_substream && snd_pcm_running(tx_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (tx_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned tx_ptr = READ_ONCE(i2s->tx_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned new_tx_ptr = i2s->tx_fn(i2s, tx_substream->runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) tx_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) cmpxchg(&i2s->tx_ptr, tx_ptr, new_tx_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return tx_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void xtfpga_pcm_refill_fifo(struct xtfpga_i2s *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) for (i = 0; i < 2; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bool tx_active = xtfpga_pcm_push_tx(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) XTFPGA_I2S_INT_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (tx_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) &int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!tx_active ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) !(int_status & XTFPGA_I2S_INT_LEVEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* After the push the level IRQ is still asserted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * means FIFO level is below tx_fifo_low. Estimate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * it as tx_fifo_low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) i2s->tx_fifo_level = i2s->tx_fifo_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!(int_status & XTFPGA_I2S_INT_LEVEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) XTFPGA_I2S_INT_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) else if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) XTFPGA_I2S_INT_UNDERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) XTFPGA_I2S_CONFIG_INT_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) XTFPGA_I2S_CONFIG_TX_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) XTFPGA_I2S_CONFIG_INT_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) XTFPGA_I2S_CONFIG_TX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) XTFPGA_I2S_CONFIG_INT_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static irqreturn_t xtfpga_i2s_threaded_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct xtfpga_i2s *i2s = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct snd_pcm_substream *tx_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned config, int_status, int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) regmap_read(i2s->regmap, XTFPGA_I2S_CONFIG, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) regmap_read(i2s->regmap, XTFPGA_I2S_INT_MASK, &int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, &int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!(config & XTFPGA_I2S_CONFIG_INT_ENABLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) !(int_status & int_mask & XTFPGA_I2S_INT_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Update FIFO level estimate in accordance with interrupt status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (int_status & XTFPGA_I2S_INT_UNDERRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) i2s->tx_fifo_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* The FIFO isn't empty, but is below tx_fifo_low. Estimate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * it as tx_fifo_low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) i2s->tx_fifo_level = i2s->tx_fifo_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) tx_substream = rcu_dereference(i2s->tx_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (tx_substream && snd_pcm_running(tx_substream)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) snd_pcm_period_elapsed(tx_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (int_status & XTFPGA_I2S_INT_UNDERRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_dbg_ratelimited(i2s->dev, "%s: underrun\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Refill FIFO, update allowed IRQ reasons, enable IRQ if FIFO is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * not empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) xtfpga_pcm_refill_fifo(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int xtfpga_i2s_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) snd_soc_dai_set_dma_data(dai, substream, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int xtfpga_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned srate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned period_size = params_period_size(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned sample_size = snd_pcm_format_width(params_format(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned freq, ratio, level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) XTFPGA_I2S_CONFIG_RES_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) sample_size << XTFPGA_I2S_CONFIG_RES_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) freq = 256 * srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) err = clk_set_rate(i2s->clk, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* ratio field of the config register controls MCLK->I2S clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * derivation: I2S clock = MCLK / (2 * (ratio + 2)).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * So with MCLK = 256 * sample rate ratio is 0 for 32 bit stereo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * and 2 for 16 bit stereo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ratio = (freq - (srate * sample_size * 8)) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) (srate * sample_size * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) XTFPGA_I2S_CONFIG_RATIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ratio << XTFPGA_I2S_CONFIG_RATIO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) i2s->tx_fifo_low = XTFPGA_I2S_FIFO_SIZE / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* period_size * 2: FIFO always gets 2 samples per frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) for (level = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) i2s->tx_fifo_low / 2 >= period_size * 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) level < (XTFPGA_I2S_CONFIG_LEVEL_MASK >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) XTFPGA_I2S_CONFIG_LEVEL_BASE); ++level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) i2s->tx_fifo_low /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) i2s->tx_fifo_high = 2 * i2s->tx_fifo_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) XTFPGA_I2S_CONFIG_LEVEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) level << XTFPGA_I2S_CONFIG_LEVEL_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_dbg(i2s->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "%s srate: %u, channels: %u, sample_size: %u, period_size: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) __func__, srate, channels, sample_size, period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_dbg(i2s->dev, "%s freq: %u, ratio: %u, level: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) __func__, freq, ratio, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int xtfpga_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const struct snd_pcm_hardware xtfpga_pcm_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .info = SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) SNDRV_PCM_INFO_BLOCK_TRANSFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .period_bytes_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .period_bytes_max = XTFPGA_I2S_FIFO_SIZE / 2 * 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .periods_max = XTFPGA_I2S_FIFO_SIZE * 8 / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .buffer_bytes_max = XTFPGA_I2S_FIFO_SIZE * 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .fifo_size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int xtfpga_pcm_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) void *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) snd_soc_set_runtime_hwparams(substream, &xtfpga_pcm_hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) p = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) runtime->private_data = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int xtfpga_pcm_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) synchronize_rcu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int xtfpga_pcm_hw_params(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct xtfpga_i2s *i2s = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned channels = params_channels(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) switch (channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) switch (params_format(hw_params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) i2s->tx_fn = (channels == 1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) xtfpga_pcm_tx_1x16 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) xtfpga_pcm_tx_2x16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) i2s->tx_fn = (channels == 1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) xtfpga_pcm_tx_1x32 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) xtfpga_pcm_tx_2x32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int xtfpga_pcm_trigger(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct xtfpga_i2s *i2s = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) WRITE_ONCE(i2s->tx_ptr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) rcu_assign_pointer(i2s->tx_substream, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) xtfpga_pcm_refill_fifo(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) rcu_assign_pointer(i2s->tx_substream, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static snd_pcm_uframes_t xtfpga_pcm_pointer(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct xtfpga_i2s *i2s = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) snd_pcm_uframes_t pos = READ_ONCE(i2s->tx_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return pos < runtime->buffer_size ? pos : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int xtfpga_pcm_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct snd_card *card = rtd->card->snd_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) size_t size = xtfpga_pcm_hardware.buffer_bytes_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) card->dev, size, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const struct snd_soc_component_driver xtfpga_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .open = xtfpga_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .close = xtfpga_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .hw_params = xtfpga_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .trigger = xtfpga_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .pointer = xtfpga_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .pcm_construct = xtfpga_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const struct snd_soc_dai_ops xtfpga_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .startup = xtfpga_i2s_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .hw_params = xtfpga_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .set_fmt = xtfpga_i2s_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static struct snd_soc_dai_driver xtfpga_i2s_dai[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .name = "xtfpga-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .rates = SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .ops = &xtfpga_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int xtfpga_i2s_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) clk_disable_unprepare(i2s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int xtfpga_i2s_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = clk_prepare_enable(i2s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int xtfpga_i2s_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct xtfpga_i2s *i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int err, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!i2s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) platform_set_drvdata(pdev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) i2s->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_dbg(&pdev->dev, "dev: %p, i2s: %p\n", &pdev->dev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) i2s->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (IS_ERR(i2s->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) err = PTR_ERR(i2s->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) &xtfpga_i2s_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (IS_ERR(i2s->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(&pdev->dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) err = PTR_ERR(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) i2s->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (IS_ERR(i2s->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_err(&pdev->dev, "couldn't get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) err = PTR_ERR(i2s->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) (0x1 << XTFPGA_I2S_CONFIG_CHANNEL_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, XTFPGA_I2S_INT_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, XTFPGA_I2S_INT_UNDERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) err = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) xtfpga_i2s_threaded_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) IRQF_SHARED | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pdev->name, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_err(&pdev->dev, "request_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) err = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) &xtfpga_i2s_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) xtfpga_i2s_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ARRAY_SIZE(xtfpga_i2s_dai));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_err(&pdev->dev, "couldn't register component\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) err = xtfpga_i2s_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_err(&pdev->dev, "%s: err = %d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int xtfpga_i2s_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct xtfpga_i2s *i2s = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (i2s->regmap && !IS_ERR(i2s->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) XTFPGA_I2S_INT_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) xtfpga_i2s_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const struct of_device_id xtfpga_i2s_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) { .compatible = "cdns,xtfpga-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MODULE_DEVICE_TABLE(of, xtfpga_i2s_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const struct dev_pm_ops xtfpga_i2s_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) SET_RUNTIME_PM_OPS(xtfpga_i2s_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) xtfpga_i2s_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct platform_driver xtfpga_i2s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .probe = xtfpga_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .remove = xtfpga_i2s_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .name = "xtfpga-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .of_match_table = of_match_ptr(xtfpga_i2s_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .pm = &xtfpga_i2s_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) module_platform_driver(xtfpga_i2s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) MODULE_DESCRIPTION("xtfpga I2S controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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