Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Xilinx ASoC SPDIF audio support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2018 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Author: Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define XLNX_SPDIF_RATES \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	(SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	SNDRV_PCM_RATE_192000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define XLNX_SPDIF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define XSPDIF_IRQ_STS_REG		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define XSPDIF_IRQ_ENABLE_REG		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define XSPDIF_SOFT_RESET_REG		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define XSPDIF_CONTROL_REG		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define XSPDIF_CHAN_0_STS_REG		0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define XSPDIF_GLOBAL_IRQ_ENABLE_REG	0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define XSPDIF_CH_A_USER_DATA_REG_0	0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define XSPDIF_CORE_ENABLE_MASK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define XSPDIF_FIFO_FLUSH_MASK		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define XSPDIF_CH_STS_MASK		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define XSPDIF_GLOBAL_IRQ_ENABLE	BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define XSPDIF_CLOCK_CONFIG_BITS_MASK	GENMASK(5, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define XSPDIF_CLOCK_CONFIG_BITS_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define XSPDIF_SOFT_RESET_VALUE		0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MAX_CHANNELS			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AES_SAMPLE_WIDTH		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CH_STATUS_UPDATE_TIMEOUT	40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) struct spdif_dev_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u32 aclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	bool rx_chsts_updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct clk *axi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	wait_queue_head_t chsts_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static irqreturn_t xlnx_spdifrx_irq_handler(int irq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct spdif_dev_data *ctx = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	val = readl(ctx->base + XSPDIF_IRQ_STS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (val & XSPDIF_CH_STS_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		writel(val & XSPDIF_CH_STS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		       ctx->base + XSPDIF_IRQ_STS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		val = readl(ctx->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			    XSPDIF_IRQ_ENABLE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		writel(val & ~XSPDIF_CH_STS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		       ctx->base + XSPDIF_IRQ_ENABLE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		ctx->rx_chsts_updated = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		wake_up_interruptible(&ctx->chsts_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int xlnx_spdif_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			      struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	val = readl(ctx->base + XSPDIF_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	val |= XSPDIF_FIFO_FLUSH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	writel(val, ctx->base + XSPDIF_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		writel(XSPDIF_CH_STS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		       ctx->base + XSPDIF_IRQ_ENABLE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		writel(XSPDIF_GLOBAL_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		       ctx->base + XSPDIF_GLOBAL_IRQ_ENABLE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static void xlnx_spdif_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	writel(XSPDIF_SOFT_RESET_VALUE, ctx->base + XSPDIF_SOFT_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int xlnx_spdif_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	u32 val, clk_div, clk_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	clk_div = DIV_ROUND_CLOSEST(ctx->aclk, MAX_CHANNELS * AES_SAMPLE_WIDTH *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				    params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	switch (clk_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		clk_cfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		clk_cfg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		clk_cfg = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		clk_cfg = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		clk_cfg = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	case 48:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		clk_cfg = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		clk_cfg = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	val = readl(ctx->base + XSPDIF_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	val &= ~XSPDIF_CLOCK_CONFIG_BITS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	val |= clk_cfg << XSPDIF_CLOCK_CONFIG_BITS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	writel(val, ctx->base + XSPDIF_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int rx_stream_detect(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	unsigned long jiffies = msecs_to_jiffies(CH_STATUS_UPDATE_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* start capture only if stream is detected within 40ms timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	err = wait_event_interruptible_timeout(ctx->chsts_q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 					       ctx->rx_chsts_updated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 					       jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		dev_err(dai->dev, "No streaming audio detected!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ctx->rx_chsts_updated = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int xlnx_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			      struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	val = readl(ctx->base + XSPDIF_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		val |= XSPDIF_CORE_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		writel(val, ctx->base + XSPDIF_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			ret = rx_stream_detect(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		val &= ~XSPDIF_CORE_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		writel(val, ctx->base + XSPDIF_CONTROL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct snd_soc_dai_ops xlnx_spdif_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.startup = xlnx_spdif_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.shutdown = xlnx_spdif_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.trigger = xlnx_spdif_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.hw_params = xlnx_spdif_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct snd_soc_dai_driver xlnx_spdif_tx_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.name = "xlnx_spdif_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.rates = XLNX_SPDIF_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.formats = XLNX_SPDIF_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.ops = &xlnx_spdif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct snd_soc_dai_driver xlnx_spdif_rx_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.name = "xlnx_spdif_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		.channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.rates = XLNX_SPDIF_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.formats = XLNX_SPDIF_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.ops = &xlnx_spdif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct snd_soc_component_driver xlnx_spdif_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.name = "xlnx-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct of_device_id xlnx_spdif_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	{ .compatible = "xlnx,spdif-2.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_DEVICE_TABLE(of, xlnx_spdif_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int xlnx_spdif_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct snd_soc_dai_driver *dai_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct spdif_dev_data *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ctx->axi_clk = devm_clk_get(dev, "s_axi_aclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (IS_ERR(ctx->axi_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		ret = PTR_ERR(ctx->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		dev_err(dev, "failed to get s_axi_aclk(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	ret = clk_prepare_enable(ctx->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		dev_err(dev, "failed to enable s_axi_aclk(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	ctx->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (IS_ERR(ctx->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		ret = PTR_ERR(ctx->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	ret = of_property_read_u32(node, "xlnx,spdif-mode", &ctx->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		dev_err(dev, "cannot get SPDIF mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (ctx->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		dai_drv = &xlnx_spdif_tx_dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			dev_err(dev, "No IRQ resource found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		ret = devm_request_irq(dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 				       xlnx_spdifrx_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 				       0, "XLNX_SPDIF_RX", ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			dev_err(dev, "spdif rx irq request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		init_waitqueue_head(&ctx->chsts_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		dai_drv = &xlnx_spdif_rx_dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	ret = of_property_read_u32(node, "xlnx,aud_clk_i", &ctx->aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		dev_err(dev, "cannot get aud_clk_i value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	dev_set_drvdata(dev, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	ret = devm_snd_soc_register_component(dev, &xlnx_spdif_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 					      dai_drv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		dev_err(dev, "SPDIF component registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	writel(XSPDIF_SOFT_RESET_VALUE, ctx->base + XSPDIF_SOFT_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	dev_info(dev, "%s DAI registered\n", dai_drv->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) clk_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	clk_disable_unprepare(ctx->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int xlnx_spdif_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	struct spdif_dev_data *ctx = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	clk_disable_unprepare(ctx->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static struct platform_driver xlnx_spdif_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		.name = "xlnx-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		.of_match_table = xlnx_spdif_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.probe = xlnx_spdif_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.remove = xlnx_spdif_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) module_platform_driver(xlnx_spdif_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MODULE_DESCRIPTION("XILINX SPDIF driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MODULE_LICENSE("GPL v2");