^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Xilinx ASoC I2S audio support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2018 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Author: Praveen Vuppala <praveenv@xilinx.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Author: Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DRV_NAME "xlnx_i2s"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define I2S_CORE_CTRL_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define I2S_I2STIM_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define I2S_CH0_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define I2S_I2STIM_VALID_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int xlnx_i2s_set_sclkout_div(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) int div_id, int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void __iomem *base = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (!div || (div & ~I2S_I2STIM_VALID_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) writel(div, base + I2S_I2STIM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int xlnx_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct snd_soc_dai *i2s_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 reg_off, chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __iomem *base = snd_soc_dai_get_drvdata(i2s_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) chan_id = params_channels(params) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) while (chan_id > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) writel(chan_id, base + reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) chan_id--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int xlnx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct snd_soc_dai *i2s_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *base = snd_soc_dai_get_drvdata(i2s_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writel(1, base + I2S_CORE_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writel(0, base + I2S_CORE_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const struct snd_soc_dai_ops xlnx_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .trigger = xlnx_i2s_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .set_clkdiv = xlnx_i2s_set_sclkout_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .hw_params = xlnx_i2s_hw_params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct snd_soc_component_driver xlnx_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct of_device_id xlnx_i2s_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { .compatible = "xlnx,i2s-transmitter-1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { .compatible = "xlnx,i2s-receiver-1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MODULE_DEVICE_TABLE(of, xlnx_i2s_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int xlnx_i2s_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct snd_soc_dai_driver *dai_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 ch, format, data_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dai_drv = devm_kzalloc(&pdev->dev, sizeof(*dai_drv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (!dai_drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = of_property_read_u32(node, "xlnx,num-channels", &ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dev_err(dev, "cannot get supported channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ch = ch * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = of_property_read_u32(node, "xlnx,dwidth", &data_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_err(dev, "cannot get data width\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) switch (data_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) format = SNDRV_PCM_FMTBIT_S16_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) format = SNDRV_PCM_FMTBIT_S24_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (of_device_is_compatible(node, "xlnx,i2s-transmitter-1.0")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dai_drv->name = "xlnx_i2s_playback";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dai_drv->playback.stream_name = "Playback";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dai_drv->playback.formats = format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dai_drv->playback.channels_min = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dai_drv->playback.channels_max = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dai_drv->playback.rates = SNDRV_PCM_RATE_8000_192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dai_drv->ops = &xlnx_i2s_dai_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) } else if (of_device_is_compatible(node, "xlnx,i2s-receiver-1.0")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dai_drv->name = "xlnx_i2s_capture";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dai_drv->capture.stream_name = "Capture";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dai_drv->capture.formats = format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dai_drv->capture.channels_min = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dai_drv->capture.channels_max = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dai_drv->capture.rates = SNDRV_PCM_RATE_8000_192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dai_drv->ops = &xlnx_i2s_dai_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_set_drvdata(&pdev->dev, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = devm_snd_soc_register_component(&pdev->dev, &xlnx_i2s_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dai_drv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_err(&pdev->dev, "i2s component registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_info(&pdev->dev, "%s DAI registered\n", dai_drv->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static struct platform_driver xlnx_i2s_aud_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .of_match_table = xlnx_i2s_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .probe = xlnx_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) module_platform_driver(xlnx_i2s_aud_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MODULE_AUTHOR("Praveen Vuppala <praveenv@xilinx.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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