^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) ST-Ericsson SA 2012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Roger Nilsson <roger.xr.nilsson@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * for ST-Ericsson.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License terms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_data/dma-ste-dma40.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "ux500_msp_i2s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "ux500_pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UX500_PLATFORM_PERIODS_BYTES_MIN 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UX500_PLATFORM_PERIODS_BYTES_MAX (64 * PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UX500_PLATFORM_PERIODS_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UX500_PLATFORM_PERIODS_MAX 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UX500_PLATFORM_BUFFER_BYTES_MAX (2048 * PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct snd_pcm_hardware ux500_pcm_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .info = SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SNDRV_PCM_INFO_RESUME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SNDRV_PCM_INFO_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .buffer_bytes_max = UX500_PLATFORM_BUFFER_BYTES_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .period_bytes_min = UX500_PLATFORM_PERIODS_BYTES_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .period_bytes_max = UX500_PLATFORM_PERIODS_BYTES_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .periods_min = UX500_PLATFORM_PERIODS_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .periods_max = UX500_PLATFORM_PERIODS_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct dma_chan *ux500_pcm_request_chan(struct snd_soc_pcm_runtime *rtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u16 per_data_width, mem_data_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct stedma40_chan_cfg *dma_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct ux500_msp_dma_params *dma_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dma_params = snd_soc_dai_get_dma_data(dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dma_cfg = dma_params->dma_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mem_data_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) switch (dma_params->data_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) per_data_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) per_data_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) per_data_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) per_data_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) dma_cfg->src_info.data_width = mem_data_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dma_cfg->dst_info.data_width = per_data_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dma_cfg->src_info.data_width = per_data_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dma_cfg->dst_info.data_width = mem_data_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return snd_dmaengine_pcm_request_channel(stedma40_filter, dma_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int ux500_pcm_prepare_slave_config(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct dma_slave_config *slave_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct msp_i2s_platform_data *pdata = asoc_rtd_to_cpu(rtd, 0)->dev->platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct snd_dmaengine_dai_dma_data *snd_dma_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct ux500_msp_dma_params *ste_dma_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ste_dma_params =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dma_addr = ste_dma_params->tx_rx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) snd_dma_params =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dma_addr = snd_dma_params->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = snd_hwparams_to_dma_slave_config(substream, params, slave_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) slave_config->dst_maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) slave_config->src_maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) slave_config->dst_addr = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) slave_config->src_addr = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct snd_dmaengine_pcm_config ux500_dmaengine_pcm_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .pcm_hardware = &ux500_pcm_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .compat_request_channel = ux500_pcm_request_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .prealloc_buffer_size = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .prepare_slave_config = ux500_pcm_prepare_slave_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct snd_dmaengine_pcm_config ux500_dmaengine_of_pcm_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .compat_request_channel = ux500_pcm_request_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .prepare_slave_config = ux500_pcm_prepare_slave_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int ux500_pcm_register_platform(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct snd_dmaengine_pcm_config *pcm_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pcm_config = &ux500_dmaengine_of_pcm_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pcm_config = &ux500_dmaengine_pcm_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = snd_dmaengine_pcm_register(&pdev->dev, pcm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) SND_DMAENGINE_PCM_FLAG_COMPAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "%s: ERROR: Failed to register platform '%s' (%d)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) __func__, pdev->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) EXPORT_SYMBOL_GPL(ux500_pcm_register_platform);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int ux500_pcm_unregister_platform(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) snd_dmaengine_pcm_unregister(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) EXPORT_SYMBOL_GPL(ux500_pcm_unregister_platform);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MODULE_AUTHOR("Ola Lilja");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MODULE_AUTHOR("Roger Nilsson");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MODULE_DESCRIPTION("ASoC UX500 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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