^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Socionext UniPhier AIO ALSA driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016-2018 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef SND_UNIPHIER_AIO_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define SND_UNIPHIER_AIO_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum ID_PORT_TYPE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PORT_TYPE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PORT_TYPE_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PORT_TYPE_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PORT_TYPE_EVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PORT_TYPE_CONV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) enum ID_PORT_DIR {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PORT_DIR_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PORT_DIR_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum IEC61937_PC {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) IEC61937_PC_AC3 = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) IEC61937_PC_PAUSE = 0x0003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) IEC61937_PC_MPA = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) IEC61937_PC_MP3 = 0x0005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) IEC61937_PC_DTS1 = 0x000b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) IEC61937_PC_DTS2 = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) IEC61937_PC_DTS3 = 0x000d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) IEC61937_PC_AAC = 0x0007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* IEC61937 Repetition period of data-burst in IEC60958 frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IEC61937_FRM_STR_AC3 1536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IEC61937_FRM_STR_MPA 1152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IEC61937_FRM_STR_MP3 1152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IEC61937_FRM_STR_DTS1 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IEC61937_FRM_STR_DTS2 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IEC61937_FRM_STR_DTS3 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IEC61937_FRM_STR_AAC 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* IEC61937 Repetition period of Pause data-burst in IEC60958 frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IEC61937_FRM_PAU_AC3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IEC61937_FRM_PAU_MPA 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IEC61937_FRM_PAU_MP3 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IEC61937_FRM_PAU_DTS1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IEC61937_FRM_PAU_DTS2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IEC61937_FRM_PAU_DTS3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IEC61937_FRM_PAU_AAC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* IEC61937 Pa and Pb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IEC61937_HEADER_SIGN 0x1f4e72f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AUD_HW_PCMIN1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AUD_HW_PCMIN2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AUD_HW_PCMIN3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AUD_HW_IECIN1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AUD_HW_DIECIN1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AUD_NAME_PCMIN1 "aio-pcmin1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AUD_NAME_PCMIN2 "aio-pcmin2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AUD_NAME_PCMIN3 "aio-pcmin3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AUD_NAME_IECIN1 "aio-iecin1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AUD_NAME_DIECIN1 "aio-diecin1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AUD_HW_HPCMOUT1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AUD_HW_PCMOUT1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AUD_HW_PCMOUT2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AUD_HW_PCMOUT3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AUD_HW_EPCMOUT1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AUD_HW_EPCMOUT2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AUD_HW_EPCMOUT3 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AUD_HW_EPCMOUT6 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AUD_HW_HIECOUT1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AUD_HW_IECOUT1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AUD_HW_CMASTER 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AUD_NAME_HPCMOUT1 "aio-hpcmout1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AUD_NAME_PCMOUT1 "aio-pcmout1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AUD_NAME_PCMOUT2 "aio-pcmout2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AUD_NAME_PCMOUT3 "aio-pcmout3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AUD_NAME_EPCMOUT1 "aio-epcmout1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AUD_NAME_EPCMOUT2 "aio-epcmout2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AUD_NAME_EPCMOUT3 "aio-epcmout3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AUD_NAME_EPCMOUT6 "aio-epcmout6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AUD_NAME_HIECOUT1 "aio-hiecout1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AUD_NAME_IECOUT1 "aio-iecout1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AUD_NAME_CMASTER "aio-cmaster"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AUD_NAME_HIECCOMPOUT1 "aio-hieccompout1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AUD_NAME_IECCOMPOUT1 "aio-ieccompout1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AUD_GNAME_HDMI "aio-hdmi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AUD_GNAME_LINE "aio-line"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AUD_GNAME_AUX "aio-aux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AUD_GNAME_IEC "aio-iec"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AUD_CLK_IO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AUD_CLK_A1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AUD_CLK_F1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AUD_CLK_A2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AUD_CLK_F2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AUD_CLK_A 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AUD_CLK_F 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AUD_CLK_APLL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AUD_CLK_RX0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AUD_CLK_USB0 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AUD_CLK_HSC0 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AUD_PLL_A1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AUD_PLL_F1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AUD_PLL_A2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AUD_PLL_F2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AUD_PLL_APLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AUD_PLL_RX0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AUD_PLL_USB0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AUD_PLL_HSC0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AUD_PLLDIV_1_2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AUD_PLLDIV_1_3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AUD_PLLDIV_1_1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AUD_PLLDIV_2_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AUD_VOL_INIT 0x4000 /* +0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AUD_VOL_MAX 0xffff /* +6dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AUD_VOL_FADE_TIME 20 /* 20ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AUD_RING_SIZE (128 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AUD_MIN_FRAGMENT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AUD_MAX_FRAGMENT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AUD_MIN_FRAGMENT_SIZE (4 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AUD_MAX_FRAGMENT_SIZE (16 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* max 5 slots, 10 channels, 2 channel in 1 slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AUD_MAX_SLOTSEL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * This is a selector for virtual register map of AIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * map: Specify the index of virtual register map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * hw : Specify the ID of real register map, selector uses this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * A meaning of this value depends specification of SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct uniphier_aio_selector {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * 'SoftWare MAPping' setting of UniPhier AIO registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * We have to setup 'virtual' register maps to access 'real' registers of AIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * This feature is legacy and meaningless but AIO needs this to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Each hardware blocks have own virtual register maps as following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Address Virtual Real
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * ------- --------- ---------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * 0x12000 DMAC map0 --> [selector] --> DMAC hardware 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * 0x12080 DMAC map1 --> [selector] --> DMAC hardware 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * 0x42000 Port map0 --> [selector] --> Port hardware 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * 0x42400 Port map1 --> [selector] --> Port hardware 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * ch : Input or output channel of DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * rb : Ring buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * iport: PCM input port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * iif : Input interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * oport: PCM output port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * oif : Output interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * och : Output channel of DMAC for sampling rate converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * These are examples for sound data paths:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * For caputure device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * (outer of AIO) -> iport -> iif -> ch -> rb -> (CPU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * For playback device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * (CPU) -> rb -> ch -> oif -> oport -> (outer of AIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * For sampling rate converter device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * (CPU) -> rb -> ch -> oif -> (HW SRC) -> iif -> och -> orb -> (CPU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct uniphier_aio_swmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct uniphier_aio_selector ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct uniphier_aio_selector rb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct uniphier_aio_selector iport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct uniphier_aio_selector iif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct uniphier_aio_selector oport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct uniphier_aio_selector oif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct uniphier_aio_selector och;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct uniphier_aio_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) const char *gname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct uniphier_aio_swmap swm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct uniphier_aio_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct uniphier_aio_chip_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) const struct uniphier_aio_spec *specs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int num_specs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const struct uniphier_aio_pll *plls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int num_plls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct snd_soc_dai_driver *dais;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int num_dais;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* DMA access mode, this is workaround for DMA hungup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int addr_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct uniphier_aio_sub {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct uniphier_aio *aio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Guard sub->rd_offs and wr_offs from IRQ handler. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) const struct uniphier_aio_swmap *swm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) const struct uniphier_aio_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* For PCM audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct snd_pcm_hw_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* For compress audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct snd_compr_stream *cstream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct snd_compr_params cparams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned char *compr_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dma_addr_t compr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) size_t compr_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int pass_through;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) enum IEC61937_PC iec_pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) bool iec_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Both PCM and compress audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) bool use_mmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u64 rd_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u64 wr_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u64 rd_org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u64 wr_org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u64 rd_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u64 wr_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct uniphier_aio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct uniphier_aio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct uniphier_aio_sub sub[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Set one of AUD_CLK_X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int clk_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int clk_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Set one of AUD_PLL_X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int pll_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int pll_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Set one of AUD_PLLDIV_X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int plldiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct uniphier_aio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) const struct uniphier_aio_chip_spec *chip_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct uniphier_aio *aios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int num_aios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int num_wup_aios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct uniphier_aio_pll *plls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int num_plls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct regmap *regmap_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static inline struct uniphier_aio *uniphier_priv(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct uniphier_aio_chip *chip = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return &chip->aios[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int uniphier_aiodma_soc_register_platform(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) extern const struct snd_compress_ops uniphier_aio_compress_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int uniphier_aio_dai_probe(struct snd_soc_dai *dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int uniphier_aio_dai_remove(struct snd_soc_dai *dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int uniphier_aio_probe(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int uniphier_aio_remove(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) extern const struct snd_soc_dai_ops uniphier_aio_i2s_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) extern const struct snd_soc_dai_ops uniphier_aio_spdif_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u64 aio_rb_cnt(struct uniphier_aio_sub *sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u64 aio_rbt_cnt_to_end(struct uniphier_aio_sub *sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u64 aio_rb_space(struct uniphier_aio_sub *sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u64 aio_rb_space_to_end(struct uniphier_aio_sub *sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) void aio_iecout_set_enable(struct uniphier_aio_chip *chip, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int aio_chip_set_pll(struct uniphier_aio_chip *chip, int pll_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) void aio_chip_init(struct uniphier_aio_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int aio_init(struct uniphier_aio_sub *sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void aio_port_reset(struct uniphier_aio_sub *sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int aio_port_set_param(struct uniphier_aio_sub *sub, int pass_through,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) const struct snd_pcm_hw_params *params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void aio_port_set_enable(struct uniphier_aio_sub *sub, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int aio_port_get_volume(struct uniphier_aio_sub *sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) void aio_port_set_volume(struct uniphier_aio_sub *sub, int vol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int aio_if_set_param(struct uniphier_aio_sub *sub, int pass_through);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int aio_oport_set_stream_type(struct uniphier_aio_sub *sub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) enum IEC61937_PC pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void aio_src_reset(struct uniphier_aio_sub *sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int aio_src_set_param(struct uniphier_aio_sub *sub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) const struct snd_pcm_hw_params *params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int aio_srcif_set_param(struct uniphier_aio_sub *sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int aio_srcch_set_param(struct uniphier_aio_sub *sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) void aio_srcch_set_enable(struct uniphier_aio_sub *sub, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int aiodma_ch_set_param(struct uniphier_aio_sub *sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) void aiodma_ch_set_enable(struct uniphier_aio_sub *sub, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int aiodma_rb_set_threshold(struct uniphier_aio_sub *sub, u64 size, u32 th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int aiodma_rb_set_buffer(struct uniphier_aio_sub *sub, u64 start, u64 end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) void aiodma_rb_sync(struct uniphier_aio_sub *sub, u64 start, u64 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) bool aiodma_rb_is_irq(struct uniphier_aio_sub *sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) void aiodma_rb_clear_irq(struct uniphier_aio_sub *sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #endif /* SND_UNIPHIER_AIO_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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