^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Socionext UniPhier AIO ALSA driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016-2018 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef SND_UNIPHIER_AIO_REG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define SND_UNIPHIER_AIO_REG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* soc-glue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SG_AOUTEN 0x1c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* SW view */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define A2CHNMAPCTR0(n) (0x00000 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define A2RBNMAPCTR0(n) (0x01000 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define A2IPORTNMAPCTR0(n) (0x02000 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define A2IPORTNMAPCTR1(n) (0x02004 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define A2IIFNMAPCTR0(n) (0x03000 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define A2OPORTNMAPCTR0(n) (0x04000 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define A2OPORTNMAPCTR1(n) (0x04004 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define A2OPORTNMAPCTR2(n) (0x04008 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define A2OIFNMAPCTR0(n) (0x05000 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define A2ATNMAPCTR0(n) (0x06000 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MAPCTR0_EN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define A2APLLCTR0 0x07000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define A2APLLCTR0_APLLXPOW_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define A2APLLCTR0_APLLXPOW_PWOFF (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define A2APLLCTR0_APLLXPOW_PWON (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define A2APLLCTR1 0x07004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define A2APLLCTR1_APLLX_MASK 0x00010101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define A2APLLCTR1_APLLX_36MHZ 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define A2APLLCTR1_APLLX_33MHZ 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define A2EXMCLKSEL0 0x07030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define A2EXMCLKSEL0_EXMCLK_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define A2EXMCLKSEL0_EXMCLK_OUTPUT (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define A2EXMCLKSEL0_EXMCLK_INPUT (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define A2SSIFSW 0x07050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define A2CH22_2CTR 0x07054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define A2AIOINPUTSEL 0x070e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define A2AIOINPUTSEL_RXSEL_PCMI1_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define A2AIOINPUTSEL_RXSEL_PCMI1_HDMIRX1 (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define A2AIOINPUTSEL_RXSEL_PCMI2_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define A2AIOINPUTSEL_RXSEL_PCMI2_SIF (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define A2AIOINPUTSEL_RXSEL_PCMI3_MASK GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define A2AIOINPUTSEL_RXSEL_PCMI3_EVEA (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define A2AIOINPUTSEL_RXSEL_IECI1_MASK GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define A2AIOINPUTSEL_RXSEL_IECI1_HDMIRX1 (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define A2AIOINPUTSEL_RXSEL_MASK (A2AIOINPUTSEL_RXSEL_PCMI1_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) A2AIOINPUTSEL_RXSEL_PCMI2_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) A2AIOINPUTSEL_RXSEL_PCMI3_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) A2AIOINPUTSEL_RXSEL_IECI1_HDMIRX1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* INTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define INTCHIM(m) (0x9028 + 0x80 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define INTRBIM(m) (0x9030 + 0x80 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define INTCHID(m) (0xa028 + 0x80 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define INTRBID(m) (0xa030 + 0x80 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* AIN(PCMINN) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IPORTMXCTR1(n) (0x22000 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IPORTMXCTR1_LRSEL_MASK GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IPORTMXCTR1_LRSEL_RIGHT (0x0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IPORTMXCTR1_LRSEL_LEFT (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IPORTMXCTR1_LRSEL_I2S (0x2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IPORTMXCTR1_OUTBITSEL_MASK (0x800003U << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IPORTMXCTR1_OUTBITSEL_32 (0x800000U << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IPORTMXCTR1_OUTBITSEL_24 (0x000000U << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IPORTMXCTR1_OUTBITSEL_20 (0x000001U << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IPORTMXCTR1_OUTBITSEL_16 (0x000002U << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IPORTMXCTR1_CHSEL_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IPORTMXCTR1_CHSEL_ALL (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IPORTMXCTR1_CHSEL_D0_D2 (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IPORTMXCTR1_CHSEL_D0 (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IPORTMXCTR1_CHSEL_D1 (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IPORTMXCTR1_CHSEL_D2 (0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IPORTMXCTR1_CHSEL_DMIX (0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IPORTMXCTR1_FSSEL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IPORTMXCTR1_FSSEL_48 (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IPORTMXCTR1_FSSEL_96 (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IPORTMXCTR1_FSSEL_192 (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IPORTMXCTR1_FSSEL_32 (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IPORTMXCTR1_FSSEL_44_1 (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IPORTMXCTR1_FSSEL_88_2 (0x5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IPORTMXCTR1_FSSEL_176_4 (0x6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IPORTMXCTR1_FSSEL_16 (0x8 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IPORTMXCTR1_FSSEL_22_05 (0x9 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IPORTMXCTR1_FSSEL_24 (0xa << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IPORTMXCTR1_FSSEL_8 (0xb << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IPORTMXCTR1_FSSEL_11_025 (0xc << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IPORTMXCTR1_FSSEL_12 (0xd << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IPORTMXCTR2(n) (0x22004 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IPORTMXCTR2_ACLKSEL_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IPORTMXCTR2_ACLKSEL_A1 (0x0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IPORTMXCTR2_ACLKSEL_F1 (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IPORTMXCTR2_ACLKSEL_A2 (0x2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IPORTMXCTR2_ACLKSEL_F2 (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IPORTMXCTR2_ACLKSEL_A2PLL (0x4 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IPORTMXCTR2_ACLKSEL_RX1 (0x5 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IPORTMXCTR2_ACLKSEL_RX2 (0x6 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IPORTMXCTR2_MSSEL_MASK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IPORTMXCTR2_MSSEL_SLAVE (0x0 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IPORTMXCTR2_MSSEL_MASTER (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IPORTMXCTR2_EXTLSIFSSEL_MASK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IPORTMXCTR2_EXTLSIFSSEL_36 (0x0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IPORTMXCTR2_EXTLSIFSSEL_24 (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IPORTMXCTR2_DACCKSEL_MASK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IPORTMXCTR2_DACCKSEL_1_2 (0x0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IPORTMXCTR2_DACCKSEL_1_3 (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IPORTMXCTR2_DACCKSEL_1_1 (0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IPORTMXCTR2_DACCKSEL_2_3 (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IPORTMXCTR2_REQEN_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IPORTMXCTR2_REQEN_DISABLE (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IPORTMXCTR2_REQEN_ENABLE (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IPORTMXCNTCTR(n) (0x22010 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IPORTMXCOUNTER(n) (0x22014 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IPORTMXCNTMONI(n) (0x22018 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IPORTMXACLKSEL0EX(n) (0x22020 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IPORTMXACLKSEL0EX_ACLKSEL0EX_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IPORTMXACLKSEL0EX_ACLKSEL0EX_INTERNAL (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IPORTMXACLKSEL0EX_ACLKSEL0EX_EXTERNAL (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IPORTMXEXNOE(n) (0x22070 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IPORTMXEXNOE_PCMINOE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IPORTMXEXNOE_PCMINOE_OUTPUT (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IPORTMXEXNOE_PCMINOE_INPUT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IPORTMXMASK(n) (0x22078 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IPORTMXMASK_IUXCKMSK_MASK GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IPORTMXMASK_IUXCKMSK_ON (0x0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IPORTMXMASK_IUXCKMSK_OFF (0x7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IPORTMXMASK_XCKMSK_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IPORTMXMASK_XCKMSK_ON (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IPORTMXMASK_XCKMSK_OFF (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IPORTMXRSTCTR(n) (0x2207c + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IPORTMXRSTCTR_RSTPI_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IPORTMXRSTCTR_RSTPI_RELEASE (0x0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IPORTMXRSTCTR_RSTPI_RESET (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* AIN(PBinMX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PBINMXCTR(n) (0x20200 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PBINMXCTR_NCONNECT_MASK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PBINMXCTR_NCONNECT_CONNECT (0x0 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PBINMXCTR_NCONNECT_DISCONNECT (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PBINMXCTR_INOUTSEL_MASK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PBINMXCTR_INOUTSEL_IN (0x0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PBINMXCTR_INOUTSEL_OUT (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PBINMXCTR_PBINSEL_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PBINMXCTR_ENDIAN_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PBINMXCTR_ENDIAN_3210 (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PBINMXCTR_ENDIAN_0123 (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PBINMXCTR_ENDIAN_1032 (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PBINMXCTR_ENDIAN_2301 (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PBINMXCTR_MEMFMT_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PBINMXCTR_MEMFMT_D0 (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PBINMXCTR_MEMFMT_5_1CH_DMIX (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PBINMXCTR_MEMFMT_6CH (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PBINMXCTR_MEMFMT_4CH (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PBINMXCTR_MEMFMT_DMIX (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PBINMXCTR_MEMFMT_1CH (0x5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PBINMXCTR_MEMFMT_16LR (0x6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PBINMXCTR_MEMFMT_7_1CH (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PBINMXCTR_MEMFMT_7_1CH_DMIX (0x8 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PBINMXCTR_MEMFMT_STREAM (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PBINMXPAUSECTR0(n) (0x20204 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PBINMXPAUSECTR1(n) (0x20208 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* AOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AOUTFADECTR0 0x40020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define AOUTENCTR0 0x40040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AOUTENCTR1 0x40044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define AOUTENCTR2 0x40048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AOUTRSTCTR0 0x40060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AOUTRSTCTR1 0x40064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AOUTRSTCTR2 0x40068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define AOUTSRCRSTCTR0 0x400c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AOUTSRCRSTCTR1 0x400c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AOUTSRCRSTCTR2 0x400c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* AOUT PCMOUT has 5 slots, slot0-3: D0-3, slot4: DMIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OPORT_SLOT_MAX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* AOUT(PCMOUTN) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OPORTMXCTR1(n) (0x42000 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define OPORTMXCTR1_I2SLRSEL_MASK (0x11 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OPORTMXCTR1_I2SLRSEL_RIGHT (0x00 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OPORTMXCTR1_I2SLRSEL_LEFT (0x01 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OPORTMXCTR1_I2SLRSEL_I2S (0x11 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OPORTMXCTR1_OUTBITSEL_MASK (0x800003U << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OPORTMXCTR1_OUTBITSEL_32 (0x800000U << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OPORTMXCTR1_OUTBITSEL_24 (0x000000U << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OPORTMXCTR1_OUTBITSEL_20 (0x000001U << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OPORTMXCTR1_OUTBITSEL_16 (0x000002U << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OPORTMXCTR1_FSSEL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OPORTMXCTR1_FSSEL_48 (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OPORTMXCTR1_FSSEL_96 (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OPORTMXCTR1_FSSEL_192 (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OPORTMXCTR1_FSSEL_32 (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OPORTMXCTR1_FSSEL_44_1 (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OPORTMXCTR1_FSSEL_88_2 (0x5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OPORTMXCTR1_FSSEL_176_4 (0x6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OPORTMXCTR1_FSSEL_16 (0x8 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OPORTMXCTR1_FSSEL_22_05 (0x9 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define OPORTMXCTR1_FSSEL_24 (0xa << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OPORTMXCTR1_FSSEL_8 (0xb << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define OPORTMXCTR1_FSSEL_11_025 (0xc << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OPORTMXCTR1_FSSEL_12 (0xd << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OPORTMXCTR2(n) (0x42004 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define OPORTMXCTR2_ACLKSEL_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define OPORTMXCTR2_ACLKSEL_A1 (0x0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OPORTMXCTR2_ACLKSEL_F1 (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OPORTMXCTR2_ACLKSEL_A2 (0x2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define OPORTMXCTR2_ACLKSEL_F2 (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define OPORTMXCTR2_ACLKSEL_A2PLL (0x4 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define OPORTMXCTR2_ACLKSEL_RX1 (0x5 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define OPORTMXCTR2_ACLKSEL_RX2 (0x6 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define OPORTMXCTR2_MSSEL_MASK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define OPORTMXCTR2_MSSEL_SLAVE (0x0 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define OPORTMXCTR2_MSSEL_MASTER (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define OPORTMXCTR2_EXTLSIFSSEL_MASK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define OPORTMXCTR2_EXTLSIFSSEL_36 (0x0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define OPORTMXCTR2_EXTLSIFSSEL_24 (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define OPORTMXCTR2_DACCKSEL_MASK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define OPORTMXCTR2_DACCKSEL_1_2 (0x0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define OPORTMXCTR2_DACCKSEL_1_3 (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define OPORTMXCTR2_DACCKSEL_1_1 (0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define OPORTMXCTR2_DACCKSEL_2_3 (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define OPORTMXCTR3(n) (0x42008 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define OPORTMXCTR3_IECTHUR_MASK BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define OPORTMXCTR3_IECTHUR_IECOUT (0x0 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define OPORTMXCTR3_IECTHUR_IECIN (0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define OPORTMXCTR3_SRCSEL_MASK GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define OPORTMXCTR3_SRCSEL_PCM (0x0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define OPORTMXCTR3_SRCSEL_STREAM (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define OPORTMXCTR3_SRCSEL_CDDTS (0x2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define OPORTMXCTR3_VALID_MASK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define OPORTMXCTR3_VALID_PCM (0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define OPORTMXCTR3_VALID_STREAM (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define OPORTMXCTR3_PMSEL_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define OPORTMXCTR3_PMSEL_MUTE (0x0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define OPORTMXCTR3_PMSEL_PAUSE (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define OPORTMXCTR3_PMSW_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define OPORTMXCTR3_PMSW_MUTE_OFF (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define OPORTMXCTR3_PMSW_MUTE_ON (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define OPORTMXSRC1CTR(n) (0x4200c + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define OPORTMXSRC1CTR_FSIIPNUM_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define OPORTMXSRC1CTR_THMODE_MASK BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define OPORTMXSRC1CTR_THMODE_SRC (0x0 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define OPORTMXSRC1CTR_THMODE_BYPASS (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define OPORTMXSRC1CTR_LOCK_MASK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define OPORTMXSRC1CTR_LOCK_UNLOCK (0x0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define OPORTMXSRC1CTR_LOCK_LOCK (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define OPORTMXSRC1CTR_SRCPATH_MASK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define OPORTMXSRC1CTR_SRCPATH_BYPASS (0x0 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define OPORTMXSRC1CTR_SRCPATH_CALC (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define OPORTMXSRC1CTR_SYNC_MASK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define OPORTMXSRC1CTR_SYNC_ASYNC (0x0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define OPORTMXSRC1CTR_SYNC_SYNC (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define OPORTMXSRC1CTR_FSOCK_MASK GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define OPORTMXSRC1CTR_FSOCK_44_1 (0x0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define OPORTMXSRC1CTR_FSOCK_48 (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define OPORTMXSRC1CTR_FSOCK_32 (0x2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define OPORTMXSRC1CTR_FSICK_MASK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define OPORTMXSRC1CTR_FSICK_44_1 (0x0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define OPORTMXSRC1CTR_FSICK_48 (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define OPORTMXSRC1CTR_FSICK_32 (0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define OPORTMXSRC1CTR_FSIIPSEL_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define OPORTMXSRC1CTR_FSIIPSEL_INNER (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define OPORTMXSRC1CTR_FSIIPSEL_OUTER (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OPORTMXSRC1CTR_FSISEL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define OPORTMXSRC1CTR_FSISEL_ACLK (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define OPORTMXSRC1CTR_FSISEL_DD (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define OPORTMXDSDMUTEDAT(n) (0x42020 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define OPORTMXDXDFREQMODE(n) (0x42024 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define OPORTMXDSDSEL(n) (0x42028 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define OPORTMXDSDPORT(n) (0x4202c + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define OPORTMXACLKSEL0EX(n) (0x42030 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define OPORTMXPATH(n) (0x42040 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define OPORTMXSYNC(n) (0x42044 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define OPORTMXREPET(n) (0x42050 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define OPORTMXREPET_STRLENGTH_AC3 SBF_(IEC61937_FRM_STR_AC3, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define OPORTMXREPET_STRLENGTH_MPA SBF_(IEC61937_FRM_STR_MPA, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define OPORTMXREPET_STRLENGTH_MP3 SBF_(IEC61937_FRM_STR_MP3, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define OPORTMXREPET_STRLENGTH_DTS1 SBF_(IEC61937_FRM_STR_DTS1, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define OPORTMXREPET_STRLENGTH_DTS2 SBF_(IEC61937_FRM_STR_DTS2, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define OPORTMXREPET_STRLENGTH_DTS3 SBF_(IEC61937_FRM_STR_DTS3, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define OPORTMXREPET_STRLENGTH_AAC SBF_(IEC61937_FRM_STR_AAC, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define OPORTMXREPET_PMLENGTH_AC3 SBF_(IEC61937_FRM_PAU_AC3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define OPORTMXREPET_PMLENGTH_MPA SBF_(IEC61937_FRM_PAU_MPA, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define OPORTMXREPET_PMLENGTH_MP3 SBF_(IEC61937_FRM_PAU_MP3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define OPORTMXREPET_PMLENGTH_DTS1 SBF_(IEC61937_FRM_PAU_DTS1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define OPORTMXREPET_PMLENGTH_DTS2 SBF_(IEC61937_FRM_PAU_DTS2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define OPORTMXREPET_PMLENGTH_DTS3 SBF_(IEC61937_FRM_PAU_DTS3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define OPORTMXREPET_PMLENGTH_AAC SBF_(IEC61937_FRM_PAU_AAC, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define OPORTMXPAUDAT(n) (0x42054 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define OPORTMXPAUDAT_PAUSEPC_CMN (IEC61937_PC_PAUSE << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define OPORTMXPAUDAT_PAUSEPD_AC3 (IEC61937_FRM_PAU_AC3 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define OPORTMXPAUDAT_PAUSEPD_MPA (IEC61937_FRM_PAU_MPA * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define OPORTMXPAUDAT_PAUSEPD_MP3 (IEC61937_FRM_PAU_MP3 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define OPORTMXPAUDAT_PAUSEPD_DTS1 (IEC61937_FRM_PAU_DTS1 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define OPORTMXPAUDAT_PAUSEPD_DTS2 (IEC61937_FRM_PAU_DTS2 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define OPORTMXPAUDAT_PAUSEPD_DTS3 (IEC61937_FRM_PAU_DTS3 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define OPORTMXPAUDAT_PAUSEPD_AAC (IEC61937_FRM_PAU_AAC * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define OPORTMXRATE_I(n) (0x420e4 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define OPORTMXRATE_I_EQU_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define OPORTMXRATE_I_EQU_NOTEQUAL (0x0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define OPORTMXRATE_I_EQU_EQUAL (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define OPORTMXRATE_I_SRCBPMD_MASK BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define OPORTMXRATE_I_SRCBPMD_BYPASS (0x0 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define OPORTMXRATE_I_SRCBPMD_SRC (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define OPORTMXRATE_I_LRCKSTP_MASK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define OPORTMXRATE_I_LRCKSTP_START (0x0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define OPORTMXRATE_I_LRCKSTP_STOP (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define OPORTMXRATE_I_ACLKSRC_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define OPORTMXRATE_I_ACLKSRC_APLL (0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define OPORTMXRATE_I_ACLKSRC_USB (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define OPORTMXRATE_I_ACLKSRC_HSC (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* if OPORTMXRATE_I_ACLKSRC_APLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define OPORTMXRATE_I_ACLKSEL_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define OPORTMXRATE_I_ACLKSEL_APLLA1 (0x0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define OPORTMXRATE_I_ACLKSEL_APLLF1 (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define OPORTMXRATE_I_ACLKSEL_APLLA2 (0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define OPORTMXRATE_I_ACLKSEL_APLLF2 (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define OPORTMXRATE_I_ACLKSEL_APLL (0x4 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define OPORTMXRATE_I_ACLKSEL_HDMI1 (0x5 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define OPORTMXRATE_I_ACLKSEL_HDMI2 (0x6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define OPORTMXRATE_I_ACLKSEL_AI1ADCCK (0xc << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define OPORTMXRATE_I_ACLKSEL_AI2ADCCK (0xd << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define OPORTMXRATE_I_ACLKSEL_AI3ADCCK (0xe << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define OPORTMXRATE_I_MCKSEL_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define OPORTMXRATE_I_MCKSEL_36 (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define OPORTMXRATE_I_MCKSEL_33 (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define OPORTMXRATE_I_MCKSEL_HSC27 (0xb << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define OPORTMXRATE_I_FSSEL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define OPORTMXRATE_I_FSSEL_48 (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define OPORTMXRATE_I_FSSEL_96 (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define OPORTMXRATE_I_FSSEL_192 (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define OPORTMXRATE_I_FSSEL_32 (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define OPORTMXRATE_I_FSSEL_44_1 (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define OPORTMXRATE_I_FSSEL_88_2 (0x5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define OPORTMXRATE_I_FSSEL_176_4 (0x6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define OPORTMXRATE_I_FSSEL_16 (0x8 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define OPORTMXRATE_I_FSSEL_22_05 (0x9 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define OPORTMXRATE_I_FSSEL_24 (0xa << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define OPORTMXRATE_I_FSSEL_8 (0xb << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define OPORTMXRATE_I_FSSEL_11_025 (0xc << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define OPORTMXRATE_I_FSSEL_12 (0xd << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define OPORTMXEXNOE(n) (0x420f0 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define OPORTMXMASK(n) (0x420f8 + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define OPORTMXMASK_IUDXMSK_MASK GENMASK(28, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define OPORTMXMASK_IUDXMSK_ON (0x00 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define OPORTMXMASK_IUDXMSK_OFF (0x1f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define OPORTMXMASK_IUXCKMSK_MASK GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define OPORTMXMASK_IUXCKMSK_ON (0x0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define OPORTMXMASK_IUXCKMSK_OFF (0x7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define OPORTMXMASK_DXMSK_MASK GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define OPORTMXMASK_DXMSK_ON (0x00 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define OPORTMXMASK_DXMSK_OFF (0x1f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define OPORTMXMASK_XCKMSK_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define OPORTMXMASK_XCKMSK_ON (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define OPORTMXMASK_XCKMSK_OFF (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define OPORTMXDEBUG(n) (0x420fc + 0x400 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define OPORTMXTYVOLPARA1(n, m) (0x42100 + 0x400 * (n) + 0x20 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define OPORTMXTYVOLPARA1_SLOPEU_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define OPORTMXTYVOLPARA2(n, m) (0x42104 + 0x400 * (n) + 0x20 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define OPORTMXTYVOLPARA2_FADE_MASK GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define OPORTMXTYVOLPARA2_FADE_NOOP (0x0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define OPORTMXTYVOLPARA2_FADE_FADEOUT (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define OPORTMXTYVOLPARA2_FADE_FADEIN (0x2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define OPORTMXTYVOLPARA2_TARGET_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define OPORTMXTYVOLGAINSTATUS(n, m) (0x42108 + 0x400 * (n) + 0x20 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define OPORTMXTYVOLGAINSTATUS_CUR_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define OPORTMXTYSLOTCTR(n, m) (0x42114 + 0x400 * (n) + 0x20 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define OPORTMXTYSLOTCTR_MODE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define OPORTMXTYSLOTCTR_SLOTSEL_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define OPORTMXTYSLOTCTR_SLOTSEL_SLOT0 (0x8 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define OPORTMXTYSLOTCTR_SLOTSEL_SLOT1 (0x9 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define OPORTMXTYSLOTCTR_SLOTSEL_SLOT2 (0xa << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define OPORTMXTYSLOTCTR_SLOTSEL_SLOT3 (0xb << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define OPORTMXTYSLOTCTR_SLOTSEL_SLOT4 (0xc << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define OPORTMXT0SLOTCTR_MUTEOFF_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define OPORTMXT0SLOTCTR_MUTEOFF_MUTE (0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define OPORTMXT0SLOTCTR_MUTEOFF_UNMUTE (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define OPORTMXTYRSTCTR(n, m) (0x4211c + 0x400 * (n) + 0x20 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define OPORTMXT0RSTCTR_RST_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define OPORTMXT0RSTCTR_RST_OFF (0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define OPORTMXT0RSTCTR_RST_ON (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SBF_(frame, shift) (((frame) * 2 - 1) << shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* AOUT(PBoutMX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define PBOUTMXCTR0(n) (0x40200 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define PBOUTMXCTR0_ENDIAN_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define PBOUTMXCTR0_ENDIAN_3210 (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define PBOUTMXCTR0_ENDIAN_0123 (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PBOUTMXCTR0_ENDIAN_1032 (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define PBOUTMXCTR0_ENDIAN_2301 (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define PBOUTMXCTR0_MEMFMT_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define PBOUTMXCTR0_MEMFMT_10CH (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define PBOUTMXCTR0_MEMFMT_8CH (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PBOUTMXCTR0_MEMFMT_6CH (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define PBOUTMXCTR0_MEMFMT_4CH (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PBOUTMXCTR0_MEMFMT_2CH (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define PBOUTMXCTR0_MEMFMT_STREAM (0x5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define PBOUTMXCTR0_MEMFMT_1CH (0x6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define PBOUTMXCTR1(n) (0x40204 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define PBOUTMXINTCTR(n) (0x40208 + 0x40 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* A2D(subsystem) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CDA2D_STRT0 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define CDA2D_STRT0_STOP_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CDA2D_STRT0_STOP_START (0x0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CDA2D_STRT0_STOP_STOP (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define CDA2D_STAT0 0x10020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define CDA2D_TEST 0x100a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define CDA2D_TEST_DDR_MODE_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define CDA2D_TEST_DDR_MODE_EXTON0 (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define CDA2D_TEST_DDR_MODE_EXTOFF1 (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define CDA2D_STRTADRSLOAD 0x100b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define CDA2D_CHMXCTRL1(n) (0x12000 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define CDA2D_CHMXCTRL1_INDSIZE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define CDA2D_CHMXCTRL1_INDSIZE_FINITE (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define CDA2D_CHMXCTRL1_INDSIZE_INFINITE (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define CDA2D_CHMXCTRL2(n) (0x12004 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CDA2D_CHMXSRCAMODE(n) (0x12020 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define CDA2D_CHMXDSTAMODE(n) (0x12024 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define CDA2D_CHMXAMODE_ENDIAN_MASK GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CDA2D_CHMXAMODE_ENDIAN_3210 (0x0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CDA2D_CHMXAMODE_ENDIAN_0123 (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define CDA2D_CHMXAMODE_ENDIAN_1032 (0x2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define CDA2D_CHMXAMODE_ENDIAN_2301 (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define CDA2D_CHMXAMODE_RSSEL_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define CDA2D_CHMXAMODE_AUPDT_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define CDA2D_CHMXAMODE_AUPDT_INC (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define CDA2D_CHMXAMODE_AUPDT_FIX (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define CDA2D_CHMXAMODE_TYPE_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define CDA2D_CHMXAMODE_TYPE_NORMAL (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define CDA2D_CHMXAMODE_TYPE_RING (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define CDA2D_CHMXSRCSTRTADRS(n) (0x12030 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define CDA2D_CHMXSRCSTRTADRSU(n) (0x12034 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define CDA2D_CHMXDSTSTRTADRS(n) (0x12038 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define CDA2D_CHMXDSTSTRTADRSU(n) (0x1203c + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* A2D(ring buffer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define CDA2D_RBFLUSH0 0x10040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define CDA2D_RBADRSLOAD 0x100b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define CDA2D_RDPTRLOAD 0x100b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define CDA2D_RDPTRLOAD_LSFLAG_LOAD (0x0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define CDA2D_RDPTRLOAD_LSFLAG_STORE (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define CDA2D_WRPTRLOAD 0x100bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define CDA2D_WRPTRLOAD_LSFLAG_LOAD (0x0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define CDA2D_WRPTRLOAD_LSFLAG_STORE (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define CDA2D_RBMXBGNADRS(n) (0x14000 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define CDA2D_RBMXBGNADRSU(n) (0x14004 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define CDA2D_RBMXENDADRS(n) (0x14008 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define CDA2D_RBMXENDADRSU(n) (0x1400c + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define CDA2D_RBMXBTH(n) (0x14038 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define CDA2D_RBMXRTH(n) (0x1403c + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define CDA2D_RBMXRDPTR(n) (0x14020 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define CDA2D_RBMXRDPTRU(n) (0x14024 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define CDA2D_RBMXWRPTR(n) (0x14028 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define CDA2D_RBMXWRPTRU(n) (0x1402c + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define CDA2D_RBMXPTRU_PTRU_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define CDA2D_RBMXCNFG(n) (0x14030 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define CDA2D_RBMXIR(n) (0x14014 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define CDA2D_RBMXIE(n) (0x14018 + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define CDA2D_RBMXID(n) (0x1401c + 0x80 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define CDA2D_RBMXIX_SPACE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define CDA2D_RBMXIX_REMAIN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #endif /* SND_UNIPHIER_AIO_REG_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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