Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * TXx9 SoC AC Link Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __TXX9ACLC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __TXX9ACLC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/txx9/dmac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ACCTLEN			0x00	/* control enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ACCTLDIS		0x04	/* control disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define   ACCTL_ENLINK		0x00000001	/* enable/disable AC-link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define   ACCTL_AUDODMA		0x00000100	/* AUDODMA enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define   ACCTL_AUDIDMA		0x00001000	/* AUDIDMA enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define   ACCTL_AUDOEHLT	0x00010000	/* AUDO error halt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 						   enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define   ACCTL_AUDIEHLT	0x00100000	/* AUDI error halt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 						   enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ACREGACC		0x08	/* codec register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define   ACREGACC_DAT_SHIFT	0	/* data field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define   ACREGACC_REG_SHIFT	16	/* address field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define   ACREGACC_CODECID_SHIFT	24	/* CODEC ID field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define   ACREGACC_READ		0x80000000	/* CODEC read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define   ACREGACC_WRITE	0x00000000	/* CODEC write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ACINTSTS		0x10	/* interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ACINTMSTS		0x14	/* interrupt masked status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ACINTEN			0x18	/* interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ACINTDIS		0x1c	/* interrupt disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define   ACINT_CODECRDY(n)	(0x00000001 << (n))	/* CODECn ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define   ACINT_REGACCRDY	0x00000010	/* ACREGACC ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define   ACINT_AUDOERR		0x00000100	/* AUDO underrun error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define   ACINT_AUDIERR		0x00001000	/* AUDI overrun error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ACDMASTS		0x80	/* DMA request status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define   ACDMA_AUDO		0x00000001	/* AUDODMA pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define   ACDMA_AUDI		0x00000010	/* AUDIDMA pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ACAUDODAT		0xa0	/* audio out data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ACAUDIDAT		0xb0	/* audio in data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ACREVID			0xfc	/* revision ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct txx9aclc_dmadata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	struct resource *dma_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	struct txx9dmac_slave dma_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	struct dma_chan *dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	spinlock_t dma_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	int stream; /* SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	unsigned long pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	unsigned long buffer_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	unsigned long period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	unsigned long frag_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	int frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	int frag_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	int dmacount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct txx9aclc_plat_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	u64 physbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline struct txx9aclc_plat_drvdata *txx9aclc_get_plat_drvdata(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	return dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif /* __TXX9ACLC_H */