Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Generic TXx9 ACLC platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2009 Atsushi Nemoto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on RBTX49xx patch from CELF patch archive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * (C) Copyright TOSHIBA CORPORATION 2004-2006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "txx9aclc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DRV_NAME "txx9aclc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static struct txx9aclc_soc_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct txx9aclc_dmadata dmadata[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) } txx9aclc_soc_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* REVISIT: How to find txx9aclc_drvdata from snd_ac97? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static struct txx9aclc_plat_drvdata *txx9aclc_drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int txx9aclc_dma_init(struct txx9aclc_soc_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 			     struct txx9aclc_dmadata *dmadata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static const struct snd_pcm_hardware txx9aclc_pcm_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	 * REVISIT: SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	 * needs more works for noncoherent MIPS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	.info		  = SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 			    SNDRV_PCM_INFO_BATCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			    SNDRV_PCM_INFO_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.period_bytes_min = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	.period_bytes_max = 8 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	.periods_min	  = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.periods_max	  = 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.buffer_bytes_max = 32 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static int txx9aclc_pcm_hw_params(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 				  struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 				  struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct txx9aclc_dmadata *dmadata = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	dev_dbg(component->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		"runtime->dma_area = %#lx dma_addr = %#lx dma_bytes = %zd "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		"runtime->min_align %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		(unsigned long)runtime->dma_area,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		(unsigned long)runtime->dma_addr, runtime->dma_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		runtime->min_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	dev_dbg(component->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		"periods %d period_bytes %d stream %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		params_periods(params), params_period_bytes(params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	dmadata->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	dmadata->pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int txx9aclc_pcm_prepare(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 				struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct txx9aclc_dmadata *dmadata = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	dmadata->dma_addr = runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	dmadata->buffer_bytes = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	dmadata->period_bytes = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (dmadata->buffer_bytes == dmadata->period_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		dmadata->frag_bytes = dmadata->period_bytes >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		dmadata->frags = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		dmadata->frag_bytes = dmadata->period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		dmadata->frags = dmadata->buffer_bytes / dmadata->period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	dmadata->frag_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	dmadata->pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static void txx9aclc_dma_complete(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct txx9aclc_dmadata *dmadata = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* dma completion handler cannot submit new operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	spin_lock_irqsave(&dmadata->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (dmadata->frag_count >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		dmadata->dmacount--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		if (!WARN_ON(dmadata->dmacount < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			queue_work(system_highpri_wq, &dmadata->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	spin_unlock_irqrestore(&dmadata->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) txx9aclc_dma_submit(struct txx9aclc_dmadata *dmadata, dma_addr_t buf_dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct dma_chan *chan = dmadata->dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct scatterlist sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	sg_init_table(&sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	sg_set_page(&sg, pfn_to_page(PFN_DOWN(buf_dma_addr)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		    dmadata->frag_bytes, buf_dma_addr & (PAGE_SIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	sg_dma_address(&sg) = buf_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	desc = dmaengine_prep_slave_sg(chan, &sg, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		dmadata->substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		dev_err(&chan->dev->device, "cannot prepare slave dma\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	desc->callback = txx9aclc_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	desc->callback_param = dmadata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define NR_DMA_CHAIN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void txx9aclc_dma_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct txx9aclc_dmadata *dmadata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		container_of(work, struct txx9aclc_dmadata, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct dma_chan *chan = dmadata->dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct snd_pcm_substream *substream = dmadata->substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u32 ctlbit = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		ACCTL_AUDODMA : ACCTL_AUDIDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	spin_lock_irqsave(&dmadata->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (dmadata->frag_count < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		void __iomem *base = drvdata->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		spin_unlock_irqrestore(&dmadata->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		dmaengine_terminate_all(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		/* first time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		for (i = 0; i < NR_DMA_CHAIN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			desc = txx9aclc_dma_submit(dmadata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				dmadata->dma_addr + i * dmadata->frag_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		dmadata->dmacount = NR_DMA_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		spin_lock_irqsave(&dmadata->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		__raw_writel(ctlbit, base + ACCTLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		dmadata->frag_count = NR_DMA_CHAIN % dmadata->frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		spin_unlock_irqrestore(&dmadata->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (WARN_ON(dmadata->dmacount >= NR_DMA_CHAIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		spin_unlock_irqrestore(&dmadata->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	while (dmadata->dmacount < NR_DMA_CHAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		dmadata->dmacount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		spin_unlock_irqrestore(&dmadata->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		desc = txx9aclc_dma_submit(dmadata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			dmadata->dma_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			dmadata->frag_count * dmadata->frag_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		spin_lock_irqsave(&dmadata->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		dmadata->frag_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		dmadata->frag_count %= dmadata->frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		dmadata->pos += dmadata->frag_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		dmadata->pos %= dmadata->buffer_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		if ((dmadata->frag_count * dmadata->frag_bytes) %
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		    dmadata->period_bytes == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			snd_pcm_period_elapsed(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	spin_unlock_irqrestore(&dmadata->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int txx9aclc_pcm_trigger(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 				struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct txx9aclc_dmadata *dmadata = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	void __iomem *base = drvdata->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u32 ctlbit = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		ACCTL_AUDODMA : ACCTL_AUDIDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	spin_lock_irqsave(&dmadata->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		dmadata->frag_count = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		queue_work(system_highpri_wq, &dmadata->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		__raw_writel(ctlbit, base + ACCTLDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		__raw_writel(ctlbit, base + ACCTLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	spin_unlock_irqrestore(&dmadata->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) txx9aclc_pcm_pointer(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		     struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct txx9aclc_dmadata *dmadata = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return bytes_to_frames(substream->runtime, dmadata->pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int txx9aclc_pcm_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			     struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct txx9aclc_soc_device *dev = &txx9aclc_soc_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct txx9aclc_dmadata *dmadata = &dev->dmadata[substream->stream];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	ret = snd_soc_set_runtime_hwparams(substream, &txx9aclc_pcm_hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/* ensure that buffer size is a multiple of period size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	ret = snd_pcm_hw_constraint_integer(substream->runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 					    SNDRV_PCM_HW_PARAM_PERIODS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	substream->runtime->private_data = dmadata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int txx9aclc_pcm_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			      struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct txx9aclc_dmadata *dmadata = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct dma_chan *chan = dmadata->dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	dmadata->frag_count = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	dmaengine_terminate_all(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int txx9aclc_pcm_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			    struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	struct snd_card *card = rtd->card->snd_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct snd_pcm *pcm = rtd->pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct platform_device *pdev = to_platform_device(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct txx9aclc_soc_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/* at this point onwards the AC97 component has probed and this will be valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	dev = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	dev->dmadata[0].stream = SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	dev->dmadata[1].stream = SNDRV_PCM_STREAM_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		r = platform_get_resource(pdev, IORESOURCE_DMA, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		dev->dmadata[i].dma_res = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		ret = txx9aclc_dma_init(dev, &dev->dmadata[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		card->dev, 64 * 1024, 4 * 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		if (dev->dmadata[i].dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			dma_release_channel(dev->dmadata[i].dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		dev->dmadata[i].dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static bool filter(struct dma_chan *chan, void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct txx9aclc_dmadata *dmadata = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	char *devname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	bool found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	devname = kasprintf(GFP_KERNEL, "%s.%d", dmadata->dma_res->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		(int)dmadata->dma_res->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (strcmp(dev_name(chan->device->dev), devname) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		chan->private = &dmadata->dma_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	kfree(devname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	return found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int txx9aclc_dma_init(struct txx9aclc_soc_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			     struct txx9aclc_dmadata *dmadata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	struct txx9dmac_slave *ds = &dmadata->dma_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	spin_lock_init(&dmadata->dma_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	ds->reg_width = sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (dmadata->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		ds->tx_reg = drvdata->physbase + ACAUDODAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		ds->rx_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		ds->tx_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		ds->rx_reg = drvdata->physbase + ACAUDIDAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	/* Try to grab a DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	dmadata->dma_chan = dma_request_channel(mask, filter, dmadata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (!dmadata->dma_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			"DMA channel for %s is not available\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			dmadata->stream == SNDRV_PCM_STREAM_PLAYBACK ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			"playback" : "capture");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	INIT_WORK(&dmadata->work, txx9aclc_dma_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int txx9aclc_pcm_probe(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	snd_soc_component_set_drvdata(component, &txx9aclc_soc_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void txx9aclc_pcm_remove(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	struct txx9aclc_soc_device *dev = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	void __iomem *base = drvdata->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	/* disable all FIFO DMAs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	__raw_writel(ACCTL_AUDODMA | ACCTL_AUDIDMA, base + ACCTLDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	/* dummy R/W to clear pending DMAREQ if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	__raw_writel(__raw_readl(base + ACAUDIDAT), base + ACAUDODAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		struct txx9aclc_dmadata *dmadata = &dev->dmadata[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		struct dma_chan *chan = dmadata->dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		if (chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			dmadata->frag_count = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			dmaengine_terminate_all(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 			dma_release_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		dev->dmadata[i].dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const struct snd_soc_component_driver txx9aclc_soc_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	.probe		= txx9aclc_pcm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	.remove		= txx9aclc_pcm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.open		= txx9aclc_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.close		= txx9aclc_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	.hw_params	= txx9aclc_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	.prepare	= txx9aclc_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	.trigger	= txx9aclc_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	.pointer	= txx9aclc_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	.pcm_construct	= txx9aclc_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int txx9aclc_soc_platform_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	return devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 					&txx9aclc_soc_component, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static struct platform_driver txx9aclc_pcm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 			.name = "txx9aclc-pcm-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	.probe = txx9aclc_soc_platform_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) module_platform_driver(txx9aclc_pcm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MODULE_DESCRIPTION("TXx9 ACLC Audio DMA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MODULE_LICENSE("GPL");