^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TXx9 ACLC AC97 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Atsushi Nemoto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on RBTX49xx patch from CELF patch archive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright TOSHIBA CORPORATION 2004-2006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mach-tx39xx/ioremap.h> /* for TXX9_DIRECTMAP_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "txx9aclc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AC97_DIR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AC97_RATES \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) SNDRV_PCM_RATE_8000_48000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AC97_FMTS SNDRV_PCM_FMTBIT_S16_BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AC97_FMTS SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static DECLARE_WAIT_QUEUE_HEAD(ac97_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* REVISIT: How to find txx9aclc_drvdata from snd_ac97? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static struct txx9aclc_plat_drvdata *txx9aclc_drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int txx9aclc_regready(struct txx9aclc_plat_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return __raw_readl(drvdata->base + ACINTSTS) & ACINT_REGACCRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* AC97 controller reads codec register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static unsigned short txx9aclc_ac97_read(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __iomem *base = drvdata->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (!(__raw_readl(base + ACINTSTS) & ACINT_CODECRDY(ac97->num)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) reg |= ac97->num << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dat = (reg << ACREGACC_REG_SHIFT) | ACREGACC_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __raw_writel(dat, base + ACREGACC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __raw_writel(ACINT_REGACCRDY, base + ACINTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (!wait_event_timeout(ac97_waitq, txx9aclc_regready(txx9aclc_drvdata), HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __raw_writel(ACINT_REGACCRDY, base + ACINTDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) printk(KERN_ERR "ac97 read timeout (reg %#x)\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dat = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dat = __raw_readl(base + ACREGACC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (((dat >> ACREGACC_REG_SHIFT) & 0xff) != reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) printk(KERN_ERR "reg mismatch %x with %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) dat, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) dat = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dat = (dat >> ACREGACC_DAT_SHIFT) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __raw_writel(ACINT_REGACCRDY, base + ACINTDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* AC97 controller writes to codec register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void txx9aclc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void __iomem *base = drvdata->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __raw_writel(((reg | (ac97->num << 7)) << ACREGACC_REG_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) (val << ACREGACC_DAT_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) base + ACREGACC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __raw_writel(ACINT_REGACCRDY, base + ACINTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!wait_event_timeout(ac97_waitq, txx9aclc_regready(txx9aclc_drvdata), HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "ac97 write timeout (reg %#x)\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __raw_writel(ACINT_REGACCRDY, base + ACINTDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void txx9aclc_ac97_cold_reset(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void __iomem *base = drvdata->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 ready = ACINT_CODECRDY(ac97->num) | ACINT_REGACCRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __raw_writel(ACCTL_ENLINK, base + ACCTLDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __raw_writel(ACCTL_ENLINK, base + ACCTLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* wait for primary codec ready status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __raw_writel(ready, base + ACINTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!wait_event_timeout(ac97_waitq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) (__raw_readl(base + ACINTSTS) & ready) == ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_err(&ac97->dev, "primary codec is not ready "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "(status %#x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __raw_readl(base + ACINTSTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __raw_writel(ACINT_REGACCRDY, base + ACINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __raw_writel(ready, base + ACINTDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* AC97 controller operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct snd_ac97_bus_ops txx9aclc_ac97_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .read = txx9aclc_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .write = txx9aclc_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .reset = txx9aclc_ac97_cold_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static irqreturn_t txx9aclc_ac97_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct txx9aclc_plat_drvdata *drvdata = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void __iomem *base = drvdata->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __raw_writel(__raw_readl(base + ACINTMSTS), base + ACINTDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) wake_up(&ac97_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int txx9aclc_ac97_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) txx9aclc_drvdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int txx9aclc_ac97_remove(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct txx9aclc_plat_drvdata *drvdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* disable AC-link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __raw_writel(ACCTL_ENLINK, drvdata->base + ACCTLDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) txx9aclc_drvdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct snd_soc_dai_driver txx9aclc_ac97_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .probe = txx9aclc_ac97_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .remove = txx9aclc_ac97_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .rates = AC97_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .formats = AC97_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .rates = AC97_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .formats = AC97_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct snd_soc_component_driver txx9aclc_ac97_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "txx9aclc-ac97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int txx9aclc_ac97_dev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct txx9aclc_plat_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) drvdata->base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (IS_ERR(drvdata->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return PTR_ERR(drvdata->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) platform_set_drvdata(pdev, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) drvdata->physbase = r->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (sizeof(drvdata->physbase) > sizeof(r->start) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) r->start >= TXX9_DIRECTMAP_BASE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) r->start < TXX9_DIRECTMAP_BASE + 0x400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) drvdata->physbase |= 0xf00000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) err = devm_request_irq(&pdev->dev, irq, txx9aclc_ac97_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 0, dev_name(&pdev->dev), drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) err = snd_soc_set_ac97_ops(&txx9aclc_ac97_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return devm_snd_soc_register_component(&pdev->dev, &txx9aclc_ac97_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) &txx9aclc_ac97_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int txx9aclc_ac97_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) snd_soc_set_ac97_ops(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct platform_driver txx9aclc_ac97_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .probe = txx9aclc_ac97_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .remove = txx9aclc_ac97_dev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .name = "txx9aclc-ac97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) module_platform_driver(txx9aclc_ac97_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MODULE_DESCRIPTION("TXx9 ACLC AC97 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MODULE_ALIAS("platform:txx9aclc-ac97");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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