^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * omap-mcpdm.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 - 2011 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Contact: Misael Lopez Cruz <misael.lopez@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __OMAP_MCPDM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __OMAP_MCPDM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MCPDM_REG_REVISION 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MCPDM_REG_SYSCONFIG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MCPDM_REG_IRQSTATUS_RAW 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MCPDM_REG_IRQSTATUS 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MCPDM_REG_IRQENABLE_SET 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MCPDM_REG_IRQENABLE_CLR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MCPDM_REG_IRQWAKE_EN 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MCPDM_REG_DMAENABLE_SET 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MCPDM_REG_DMAENABLE_CLR 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MCPDM_REG_DMAWAKEEN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MCPDM_REG_CTRL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MCPDM_REG_DN_DATA 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MCPDM_REG_UP_DATA 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MCPDM_REG_FIFO_CTRL_DN 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MCPDM_REG_FIFO_CTRL_UP 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MCPDM_REG_DN_OFFSET 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * MCPDM_IRQ bit fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCPDM_DN_IRQ (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCPDM_DN_IRQ_EMPTY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCPDM_DN_IRQ_ALMST_EMPTY (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MCPDM_DN_IRQ_FULL (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MCPDM_UP_IRQ (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCPDM_UP_IRQ_EMPTY (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCPDM_UP_IRQ_ALMST_FULL (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MCPDM_UP_IRQ_FULL (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MCPDM_DOWNLINK_IRQ_MASK 0x00F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MCPDM_UPLINK_IRQ_MASK 0xF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * MCPDM_DMAENABLE bit fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MCPDM_DMA_DN_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MCPDM_DMA_UP_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * MCPDM_CTRL bit fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MCPDM_PDM_UPLINK_EN(x) (1 << (x - 1)) /* ch1 is at bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MCPDM_PDM_DOWNLINK_EN(x) (1 << (x + 2)) /* ch1 is at bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MCPDM_PDMOUTFORMAT (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MCPDM_CMD_INT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MCPDM_STATUS_INT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MCPDM_SW_UP_RST (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MCPDM_SW_DN_RST (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MCPDM_WD_EN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MCPDM_PDM_UP_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MCPDM_PDM_DN_MASK (0x1f << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MCPDM_PDMOUTFORMAT_LJUST (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MCPDM_PDMOUTFORMAT_RJUST (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * MCPDM_FIFO_CTRL bit fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MCPDM_UP_THRES_MAX 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MCPDM_DN_THRES_MAX 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * MCPDM_DN_OFFSET bit fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MCPDM_DN_OFST_RX1_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MCPDM_DNOFST_RX1(x) ((x & 0x1f) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MCPDM_DN_OFST_RX2_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MCPDM_DNOFST_RX2(x) ((x & 0x1f) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 rx1, u8 rx2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif /* End of __OMAP_MCPDM_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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