^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 - 2011 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Misael Lopez Cruz <misael.lopez@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Margarita Olaya <magi.olaya@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Peter Ujfalusi <peter.ujfalusi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "omap-mcpdm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "sdma-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct mcpdm_link_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 link_mask; /* channel mask for the direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 threshold; /* FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct omap_mcpdm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct pm_qos_request pm_qos_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int latency[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Playback/Capture configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct mcpdm_link_config config[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* McPDM dn offsets for rx1, and 2 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 dn_rx_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* McPDM needs to be restarted due to runtime reconfiguration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bool restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* pm state for suspend/resume handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int pm_active_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct snd_dmaengine_dai_dma_data dma_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Stream DMA parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writel_relaxed(val, mcpdm->io_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return readl_relaxed(mcpdm->io_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dev_dbg(mcpdm->dev, "***********************\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dev_dbg(mcpdm->dev, "***********************\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Enables the transfer through the PDM interface to/from the Phoenix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * codec by enabling the corresponding UP or DN channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ctrl |= link_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * Disables the transfer through the PDM interface to/from the Phoenix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * codec by disabling the corresponding UP or DN channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ctrl &= ~(link_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Is the physical McPDM interface active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Configures McPDM uplink, and downlink for audio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * This function should be called before omap_mcpdm_start.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Enable DN RX1/2 offset cancellation feature, if configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (mcpdm->dn_rx_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 dn_offset = mcpdm->dn_rx_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Cleans McPDM uplink, and downlink configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * This function should be called when the stream is closed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Disable irq request generation for downlink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Disable DMA request generation for downlink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Disable irq request generation for uplink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Disable DMA request generation for uplink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Disable RX1/2 offset cancellation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (mcpdm->dn_rx_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct omap_mcpdm *mcpdm = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Acknowledge irq event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (irq_status & MCPDM_DN_IRQ_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (irq_status & MCPDM_DN_IRQ_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (irq_status & MCPDM_DN_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_dbg(mcpdm->dev, "DN (playback) write request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (irq_status & MCPDM_UP_IRQ_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (irq_status & MCPDM_UP_IRQ_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (irq_status & MCPDM_UP_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_dbg(mcpdm->dev, "UP (capture) write request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mutex_lock(&mcpdm->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!snd_soc_dai_active(dai))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) omap_mcpdm_open_streams(mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mutex_unlock(&mcpdm->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mutex_lock(&mcpdm->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (!snd_soc_dai_active(dai)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (omap_mcpdm_active(mcpdm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) omap_mcpdm_stop(mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) omap_mcpdm_close_streams(mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mcpdm->config[0].link_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mcpdm->config[1].link_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (mcpdm->latency[stream2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) cpu_latency_qos_update_request(&mcpdm->pm_qos_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mcpdm->latency[stream2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) else if (mcpdm->latency[stream1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) cpu_latency_qos_remove_request(&mcpdm->pm_qos_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mcpdm->latency[stream1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mutex_unlock(&mcpdm->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int stream = substream->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct snd_dmaengine_dai_dma_data *dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int channels, latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int link_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) switch (channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* up to 3 channels for capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) link_mask |= 1 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* up to 3 channels for capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) link_mask |= 1 << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) link_mask |= 1 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) link_mask |= 1 << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) link_mask |= 1 << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* unsupported number of channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dma_data = snd_soc_dai_get_dma_data(dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) threshold = mcpdm->config[stream].threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Configure McPDM channels, and DMA packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) link_mask <<= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* If capture is not running assume a stereo stream to come */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!mcpdm->config[!stream].link_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mcpdm->config[!stream].link_mask = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dma_data->maxburst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) (MCPDM_DN_THRES_MAX - threshold) * channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) latency = threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* If playback is not running assume a stereo stream to come */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!mcpdm->config[!stream].link_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mcpdm->config[!stream].link_mask = (0x3 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dma_data->maxburst = threshold * channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) latency = (MCPDM_DN_THRES_MAX - threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * The DMA must act to a DMA request within latency time (usec) to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * under/overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mcpdm->latency[stream] = latency * USEC_PER_SEC / params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (!mcpdm->latency[stream])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) mcpdm->latency[stream] = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Check if we need to restart McPDM with this stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (mcpdm->config[stream].link_mask &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mcpdm->config[stream].link_mask != link_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) mcpdm->restart = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mcpdm->config[stream].link_mask = link_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct pm_qos_request *pm_qos_req = &mcpdm->pm_qos_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int latency = mcpdm->latency[stream2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Prevent omap hardware from hitting off between FIFO fills */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!latency || mcpdm->latency[stream1] < latency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) latency = mcpdm->latency[stream1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (cpu_latency_qos_request_active(pm_qos_req))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) cpu_latency_qos_update_request(pm_qos_req, latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) else if (latency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) cpu_latency_qos_add_request(pm_qos_req, latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (!omap_mcpdm_active(mcpdm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) omap_mcpdm_start(mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) omap_mcpdm_reg_dump(mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) } else if (mcpdm->restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) omap_mcpdm_stop(mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) omap_mcpdm_start(mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mcpdm->restart = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) omap_mcpdm_reg_dump(mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .startup = omap_mcpdm_dai_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .shutdown = omap_mcpdm_dai_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .hw_params = omap_mcpdm_dai_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .prepare = omap_mcpdm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int omap_mcpdm_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pm_runtime_enable(mcpdm->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Disable lines while request is ongoing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pm_runtime_get_sync(mcpdm->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler, 0, "McPDM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) (void *)mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pm_runtime_put_sync(mcpdm->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_err(mcpdm->dev, "Request for IRQ failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pm_runtime_disable(mcpdm->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Configure McPDM threshold values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MCPDM_UP_THRES_MAX - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) snd_soc_dai_init_dma_data(dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) &mcpdm->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) &mcpdm->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int omap_mcpdm_remove(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) free_irq(mcpdm->irq, (void *)mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pm_runtime_disable(mcpdm->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (cpu_latency_qos_request_active(&mcpdm->pm_qos_req))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) cpu_latency_qos_remove_request(&mcpdm->pm_qos_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int omap_mcpdm_suspend(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct omap_mcpdm *mcpdm = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (snd_soc_component_active(component)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) omap_mcpdm_stop(mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) omap_mcpdm_close_streams(mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) mcpdm->pm_active_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) while (pm_runtime_active(mcpdm->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pm_runtime_put_sync(mcpdm->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mcpdm->pm_active_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int omap_mcpdm_resume(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct omap_mcpdm *mcpdm = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (mcpdm->pm_active_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) while (mcpdm->pm_active_count--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pm_runtime_get_sync(mcpdm->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (snd_soc_component_active(component)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) omap_mcpdm_open_streams(mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) omap_mcpdm_start(mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define omap_mcpdm_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define omap_mcpdm_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static struct snd_soc_dai_driver omap_mcpdm_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .probe = omap_mcpdm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .remove = omap_mcpdm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .probe_order = SND_SOC_COMP_ORDER_LATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .remove_order = SND_SOC_COMP_ORDER_EARLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .channels_max = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .rates = OMAP_MCPDM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .formats = OMAP_MCPDM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .sig_bits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .channels_max = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .rates = OMAP_MCPDM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .formats = OMAP_MCPDM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .sig_bits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .ops = &omap_mcpdm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const struct snd_soc_component_driver omap_mcpdm_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .name = "omap-mcpdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .suspend = omap_mcpdm_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .resume = omap_mcpdm_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u8 rx1, u8 rx2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int asoc_mcpdm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct omap_mcpdm *mcpdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (!mcpdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) platform_set_drvdata(pdev, mcpdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mutex_init(&mcpdm->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (res == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mcpdm->dma_data[0].filter_data = "dn_link";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mcpdm->dma_data[1].filter_data = "up_link";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (IS_ERR(mcpdm->io_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return PTR_ERR(mcpdm->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mcpdm->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (mcpdm->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return mcpdm->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) mcpdm->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) &omap_mcpdm_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) &omap_mcpdm_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return sdma_pcm_platform_register(&pdev->dev, "dn_link", "up_link");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const struct of_device_id omap_mcpdm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { .compatible = "ti,omap4-mcpdm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static struct platform_driver asoc_mcpdm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .name = "omap-mcpdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .of_match_table = omap_mcpdm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .probe = asoc_mcpdm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) module_platform_driver(asoc_mcpdm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MODULE_ALIAS("platform:omap-mcpdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MODULE_DESCRIPTION("OMAP PDM SoC Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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