^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP Multi-Channel Buffered Serial Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Peter Ujfalusi <peter.ujfalusi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __OMAP_MCBSP_PRIV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __OMAP_MCBSP_PRIV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_data/asoc-ti-mcbsp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifdef CONFIG_ARCH_OMAP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define mcbsp_omap1() 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define mcbsp_omap1() 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* McBSP register numbers. Register address offset = num * reg_step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Common registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) OMAP_MCBSP_REG_SPCR2 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) OMAP_MCBSP_REG_SPCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) OMAP_MCBSP_REG_RCR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) OMAP_MCBSP_REG_RCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) OMAP_MCBSP_REG_XCR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) OMAP_MCBSP_REG_XCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) OMAP_MCBSP_REG_SRGR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) OMAP_MCBSP_REG_SRGR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) OMAP_MCBSP_REG_MCR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) OMAP_MCBSP_REG_MCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) OMAP_MCBSP_REG_RCERA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) OMAP_MCBSP_REG_RCERB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) OMAP_MCBSP_REG_XCERA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) OMAP_MCBSP_REG_XCERB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) OMAP_MCBSP_REG_PCR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) OMAP_MCBSP_REG_RCERC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) OMAP_MCBSP_REG_RCERD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) OMAP_MCBSP_REG_XCERC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) OMAP_MCBSP_REG_XCERD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) OMAP_MCBSP_REG_RCERE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) OMAP_MCBSP_REG_RCERF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) OMAP_MCBSP_REG_XCERE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) OMAP_MCBSP_REG_XCERF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) OMAP_MCBSP_REG_RCERG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) OMAP_MCBSP_REG_RCERH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) OMAP_MCBSP_REG_XCERG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) OMAP_MCBSP_REG_XCERH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* OMAP1-OMAP2420 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) OMAP_MCBSP_REG_DRR2 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) OMAP_MCBSP_REG_DRR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) OMAP_MCBSP_REG_DXR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) OMAP_MCBSP_REG_DXR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* OMAP2430 and onwards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) OMAP_MCBSP_REG_DRR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) OMAP_MCBSP_REG_DXR = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) OMAP_MCBSP_REG_SYSCON = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) OMAP_MCBSP_REG_THRSH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) OMAP_MCBSP_REG_THRSH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) OMAP_MCBSP_REG_IRQST = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) OMAP_MCBSP_REG_IRQEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) OMAP_MCBSP_REG_WAKEUPEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) OMAP_MCBSP_REG_XCCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) OMAP_MCBSP_REG_RCCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) OMAP_MCBSP_REG_XBUFFSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) OMAP_MCBSP_REG_RBUFFSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) OMAP_MCBSP_REG_SSELCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /************************** McBSP SPCR1 bit definitions ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RRST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RRDY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RFULL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RSYNC_ERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ABIS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DXENA BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLKSTP(value) (((value) & 0x3) << 11) /* bits 11:12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RJUST(value) (((value) & 0x3) << 13) /* bits 13:14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ALB BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DLB BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /************************** McBSP SPCR2 bit definitions ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define XRST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define XRDY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define XEMPTY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define XSYNC_ERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define XINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GRST BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define FRST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SOFT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define FREE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /************************** McBSP PCR bit definitions *************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLKRP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLKXP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define FSRP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define FSXP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DR_STAT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DX_STAT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLKS_STAT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SCLKME BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLKRM BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLKXM BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define FSRM BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define FSXM BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RIOEN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define XIOEN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IDLE_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /************************** McBSP RCR1 bit definitions ************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /************************** McBSP XCR1 bit definitions ************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define XWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define XFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*************************** McBSP RCR2 bit definitions ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RDATDLY(value) ((value) & 0x3) /* Bits 0:1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RFIG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RPHASE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*************************** McBSP XCR2 bit definitions ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define XDATDLY(value) ((value) & 0x3) /* Bits 0:1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define XFIG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define XCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define XWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define XFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define XPHASE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /************************* McBSP SRGR1 bit definitions ************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLKGDV(value) ((value) & 0x7f) /* Bits 0:7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define FWID(value) (((value) & 0xff) << 8) /* Bits 8:15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /************************* McBSP SRGR2 bit definitions ************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FPER(value) ((value) & 0x0fff) /* Bits 0:11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FSGM BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLKSM BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLKSP BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GSYNC BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /************************* McBSP MCR1 bit definitions *************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RMCM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /************************* McBSP MCR2 bit definitions *************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define XMCM(value) ((value) & 0x3) /* Bits 0:1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define XCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define XPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define XPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*********************** McBSP XCCR bit definitions *************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define XDISABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define XDMAEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DILB BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define XFULL_CYCLE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DXENDLY(value) (((value) & 0x3) << 12) /* Bits 12:13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PPCONNECT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define EXTCLKGATE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /********************** McBSP RCCR bit definitions *************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RDISABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RDMAEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RFULL_CYCLE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /********************** McBSP SYSCONFIG bit definitions ********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SOFTRST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ENAWAKEUP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SIDLEMODE(value) (((value) & 0x3) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLOCKACTIVITY(value) (((value) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /********************** McBSP DMA operating modes **************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MCBSP_DMA_MODE_ELEMENT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MCBSP_DMA_MODE_THRESHOLD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /********************** McBSP WAKEUPEN/IRQST/IRQEN bit definitions *********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define RSYNCERREN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define RFSREN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define REOFEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define RRDYEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define RUNDFLEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ROVFLEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define XSYNCERREN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define XFSXEN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define XEOFEN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define XRDYEN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define XUNDFLEN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define XOVFLEN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define XEMPTYEOFEN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Clock signal muxing options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLKR_SRC_CLKR 0 /* CLKR signal is from the CLKR pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLKR_SRC_CLKX 1 /* CLKR signal is from the CLKX pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define FSR_SRC_FSR 2 /* FSR signal is from the FSR pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define FSR_SRC_FSX 3 /* FSR signal is from the FSX pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* McBSP functional clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MCBSP_CLKS_PRCM_SRC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MCBSP_CLKS_PAD_SRC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* we don't do multichannel for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct omap_mcbsp_reg_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u16 spcr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u16 spcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u16 rcr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u16 rcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u16 xcr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u16 xcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u16 srgr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u16 srgr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u16 mcr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u16 mcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u16 pcr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u16 rcerc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u16 rcerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u16 xcerc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u16 xcerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u16 rcere;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u16 rcerf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u16 xcere;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u16 xcerf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u16 rcerg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u16 rcerh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u16 xcerg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u16 xcerh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u16 xccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u16 rccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct omap_mcbsp_st_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct omap_mcbsp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct clk *fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned long phys_dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Flags indicating is the bus already activated and configured by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * another substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int configured;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u8 free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int rx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int tx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Protect the field .free, while checking if the mcbsp is in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct omap_mcbsp_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct omap_mcbsp_st_data *st_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct omap_mcbsp_reg_cfg cfg_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct snd_dmaengine_dai_dma_data dma_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int dma_req[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int dma_op_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u16 max_tx_thres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u16 max_rx_thres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void *reg_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int reg_cache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int in_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int latency[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int wlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct pm_qos_request pm_qos_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static inline void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (mcbsp->pdata->reg_size == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) writew_relaxed((u16)val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ((u32 *)mcbsp->reg_cache)[reg] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) writel_relaxed(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static inline int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) bool from_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (mcbsp->pdata->reg_size == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return !from_cache ? readw_relaxed(addr) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ((u16 *)mcbsp->reg_cache)[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return !from_cache ? readl_relaxed(addr) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ((u32 *)mcbsp->reg_cache)[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define MCBSP_READ(mcbsp, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MCBSP_WRITE(mcbsp, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MCBSP_READ_CACHE(mcbsp, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Sidetone specific API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int omap_mcbsp_st_init(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) void omap_mcbsp_st_cleanup(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int omap_mcbsp_st_start(struct omap_mcbsp *mcbsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int omap_mcbsp_st_stop(struct omap_mcbsp *mcbsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif /* __OMAP_MCBSP_PRIV_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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