Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * omap-dmic.h  --  OMAP Digital Microphone Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _OMAP_DMIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _OMAP_DMIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define OMAP_DMIC_REVISION_REG		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define OMAP_DMIC_SYSCONFIG_REG		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define OMAP_DMIC_IRQSTATUS_RAW_REG	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define OMAP_DMIC_IRQSTATUS_REG		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define OMAP_DMIC_IRQENABLE_SET_REG	0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define OMAP_DMIC_IRQENABLE_CLR_REG	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define OMAP_DMIC_IRQWAKE_EN_REG	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OMAP_DMIC_DMAENABLE_SET_REG	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define OMAP_DMIC_DMAENABLE_CLR_REG	0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define OMAP_DMIC_DMAWAKEEN_REG		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OMAP_DMIC_CTRL_REG		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OMAP_DMIC_DATA_REG		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OMAP_DMIC_FIFO_CTRL_REG		0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OMAP_DMIC_FIFO_DMIC1R_DATA_REG	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OMAP_DMIC_FIFO_DMIC1L_DATA_REG	0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP_DMIC_FIFO_DMIC2R_DATA_REG	0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP_DMIC_FIFO_DMIC2L_DATA_REG	0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP_DMIC_FIFO_DMIC3R_DATA_REG	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP_DMIC_FIFO_DMIC3L_DATA_REG	0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP_DMIC_IRQ			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP_DMIC_IRQ_FULL		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP_DMIC_IRQ_ALMST_EMPTY	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP_DMIC_IRQ_EMPTY		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP_DMIC_IRQ_MASK		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* DMIC_DMAENABLE bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP_DMIC_DMA_ENABLE		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* DMIC_CTRL bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP_DMIC_UP1_ENABLE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP_DMIC_UP2_ENABLE		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP_DMIC_UP3_ENABLE		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP_DMIC_UP_ENABLE_MASK	0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP_DMIC_FORMAT		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP_DMIC_POLAR1		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP_DMIC_POLAR2		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP_DMIC_POLAR3		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP_DMIC_POLAR_MASK		(0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP_DMIC_CLK_DIV(x)		(((x) & 0x7) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP_DMIC_CLK_DIV_MASK		(0x7 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define	OMAP_DMIC_RESET			(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP_DMICOUTFORMAT_LJUST	(0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP_DMICOUTFORMAT_RJUST	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* DMIC_FIFO_CTRL bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP_DMIC_THRES_MAX		0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum omap_dmic_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	OMAP_DMIC_SYSCLK_PAD_CLKS,		/* PAD_CLKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS,		/* SLIMBUS_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS,		/* DMIC_SYNC_MUX_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	OMAP_DMIC_ABE_DMIC_CLK,			/* abe_dmic_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #endif