^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * omap-dmic.c -- OMAP ASoC DMIC DAI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 - 2011 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: David Lambert <dlambert@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Misael Lopez Cruz <misael.lopez@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Liam Girdwood <lrg@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Peter Ujfalusi <peter.ujfalusi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "omap-dmic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "sdma-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct omap_dmic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct clk *fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct pm_qos_request pm_qos_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int fclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int out_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 ch_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) bool active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct snd_dmaengine_dai_dma_data dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) writel_relaxed(val, dmic->io_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return readl_relaxed(dmic->io_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline void omap_dmic_start(struct omap_dmic *dmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Configure DMA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) OMAP_DMIC_DMA_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline void omap_dmic_stop(struct omap_dmic *dmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Disable DMA request generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) OMAP_DMIC_DMA_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static inline int dmic_is_enabled(struct omap_dmic *dmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) OMAP_DMIC_UP_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mutex_lock(&dmic->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!snd_soc_dai_active(dai))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dmic->active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mutex_unlock(&dmic->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mutex_lock(&dmic->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) cpu_latency_qos_remove_request(&dmic->pm_qos_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!snd_soc_dai_active(dai))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dmic->active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mutex_unlock(&dmic->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int divider = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (sample_rate == 192000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_err(dmic->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "invalid clock configuration for 192KHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) switch (dmic->out_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case 1536000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (dmic->fclk_freq != 24576000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) goto div_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) divider = 0x4; /* Divider: 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case 2400000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) switch (dmic->fclk_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case 12000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) divider = 0x5; /* Divider: 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case 19200000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) divider = 0x0; /* Divider: 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case 24000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) divider = 0x2; /* Divider: 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) goto div_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case 3072000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (dmic->fclk_freq != 24576000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) goto div_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) divider = 0x3; /* Divider: 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case 3840000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (dmic->fclk_freq != 19200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) goto div_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_err(dmic->dev, "invalid out frequency: %dHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dmic->out_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) div_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dmic->out_freq, dmic->fclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct snd_dmaengine_dai_dma_data *dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (dmic->clk_div < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dmic->out_freq, dmic->fclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dmic->ch_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) switch (channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_err(dmic->dev, "invalid number of legacy channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* packet size is threshold * channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dma_data = snd_soc_dai_get_dma_data(dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dma_data->maxburst = dmic->threshold * channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dmic->latency = (OMAP_DMIC_THRES_MAX - dmic->threshold) * USEC_PER_SEC /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (cpu_latency_qos_request_active(&dmic->pm_qos_req))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) cpu_latency_qos_update_request(&dmic->pm_qos_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dmic->latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Configure uplink threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Set dmic out format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Configure dmic clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int cmd, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) omap_dmic_start(dmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) omap_dmic_stop(dmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct clk *parent_clk, *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) char *parent_clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) switch (freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case 12000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case 19200000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case 24000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case 24576000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dmic->fclk_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (dmic->sysclk == clk_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dmic->fclk_freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* re-parent not allowed if a stream is ongoing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (dmic->active && dmic_is_enabled(dmic)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_err(dmic->dev, "can't re-parent when DMIC active\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) switch (clk_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case OMAP_DMIC_SYSCLK_PAD_CLKS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) parent_clk_name = "pad_clks_ck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) parent_clk_name = "slimbus_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) parent_clk_name = "dmic_sync_mux_ck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) parent_clk = clk_get(dmic->dev, parent_clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (IS_ERR(parent_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mux = clk_get_parent(dmic->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (IS_ERR(mux)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_err(dmic->dev, "can't get fck mux parent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) clk_put(parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mutex_lock(&dmic->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (dmic->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* disable clock while reparenting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pm_runtime_put_sync(dmic->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = clk_set_parent(mux, parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pm_runtime_get_sync(dmic->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = clk_set_parent(mux, parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mutex_unlock(&dmic->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(dmic->dev, "re-parent failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) goto err_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dmic->sysclk = clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dmic->fclk_freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) err_busy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) clk_put(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) clk_put(parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_err(dmic->dev, "output clk_id (%d) not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) switch (freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case 1536000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) case 2400000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case 3072000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case 3840000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dmic->out_freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dmic->out_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (dir == SND_SOC_CLOCK_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return omap_dmic_select_fclk(dmic, clk_id, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) else if (dir == SND_SOC_CLOCK_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return omap_dmic_select_outclk(dmic, clk_id, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .startup = omap_dmic_dai_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .shutdown = omap_dmic_dai_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .hw_params = omap_dmic_dai_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .prepare = omap_dmic_dai_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .trigger = omap_dmic_dai_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .set_sysclk = omap_dmic_set_dai_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int omap_dmic_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pm_runtime_enable(dmic->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Disable lines while request is ongoing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pm_runtime_get_sync(dmic->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pm_runtime_put_sync(dmic->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Configure DMIC threshold value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) snd_soc_dai_init_dma_data(dai, NULL, &dmic->dma_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int omap_dmic_remove(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pm_runtime_disable(dmic->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static struct snd_soc_dai_driver omap_dmic_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .name = "omap-dmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .probe = omap_dmic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .remove = omap_dmic_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .channels_max = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .formats = SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .sig_bits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .ops = &omap_dmic_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct snd_soc_component_driver omap_dmic_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .name = "omap-dmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int asoc_dmic_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct omap_dmic *dmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!dmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) platform_set_drvdata(pdev, dmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dmic->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mutex_init(&dmic->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dmic->fclk = devm_clk_get(dmic->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (IS_ERR(dmic->fclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(dmic->dev, "cant get fck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_err(dmic->dev, "invalid dma memory resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dmic->dma_data.addr = res->start + OMAP_DMIC_DATA_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dmic->dma_data.filter_data = "up_link";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (IS_ERR(dmic->io_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return PTR_ERR(dmic->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) &omap_dmic_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) &omap_dmic_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ret = sdma_pcm_platform_register(&pdev->dev, NULL, "up_link");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static const struct of_device_id omap_dmic_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) { .compatible = "ti,omap4-dmic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MODULE_DEVICE_TABLE(of, omap_dmic_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static struct platform_driver asoc_dmic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .name = "omap-dmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .of_match_table = omap_dmic_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .probe = asoc_dmic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) module_platform_driver(asoc_dmic_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MODULE_ALIAS("platform:omap-dmic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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