Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * ALSA SoC McASP Audio Layer for TI DAVINCI processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * MCASP related definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Nirmal Pandey <n-pandey@ti.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *         Suresh Rajashekara <suresh.r@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *         Steve Chen <schen@.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Copyright:   (C) 2009  Texas Instruments, India
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #ifndef DAVINCI_MCASP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DAVINCI_MCASP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * McASP register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DAVINCI_MCASP_PID_REG		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DAVINCI_MCASP_PWREMUMGT_REG	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DAVINCI_MCASP_PFUNC_REG		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DAVINCI_MCASP_PDIR_REG		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DAVINCI_MCASP_PDOUT_REG		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define DAVINCI_MCASP_PDSET_REG		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DAVINCI_MCASP_PDCLR_REG		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DAVINCI_MCASP_TLGC_REG		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DAVINCI_MCASP_TLMR_REG		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DAVINCI_MCASP_GBLCTL_REG	0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DAVINCI_MCASP_AMUTE_REG		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DAVINCI_MCASP_LBCTL_REG		0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DAVINCI_MCASP_TXDITCTL_REG	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DAVINCI_MCASP_GBLCTLR_REG	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DAVINCI_MCASP_RXMASK_REG	0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DAVINCI_MCASP_RXFMT_REG		0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DAVINCI_MCASP_RXFMCTL_REG	0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DAVINCI_MCASP_ACLKRCTL_REG	0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DAVINCI_MCASP_AHCLKRCTL_REG	0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define DAVINCI_MCASP_RXTDM_REG		0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define DAVINCI_MCASP_EVTCTLR_REG	0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DAVINCI_MCASP_RXSTAT_REG	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define DAVINCI_MCASP_RXTDMSLOT_REG	0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define DAVINCI_MCASP_RXCLKCHK_REG	0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define DAVINCI_MCASP_REVTCTL_REG	0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define DAVINCI_MCASP_GBLCTLX_REG	0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define DAVINCI_MCASP_TXMASK_REG	0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define DAVINCI_MCASP_TXFMT_REG		0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define DAVINCI_MCASP_TXFMCTL_REG	0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define DAVINCI_MCASP_ACLKXCTL_REG	0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define DAVINCI_MCASP_AHCLKXCTL_REG	0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define DAVINCI_MCASP_TXTDM_REG		0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define DAVINCI_MCASP_EVTCTLX_REG	0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define DAVINCI_MCASP_TXSTAT_REG	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define DAVINCI_MCASP_TXTDMSLOT_REG	0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DAVINCI_MCASP_TXCLKCHK_REG	0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define DAVINCI_MCASP_XEVTCTL_REG	0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* Left(even TDM Slot) Channel Status Register File */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define DAVINCI_MCASP_DITCSRA_REG	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* Right(odd TDM slot) Channel Status Register File */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DAVINCI_MCASP_DITCSRB_REG	0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* Left(even TDM slot) User Data Register File */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DAVINCI_MCASP_DITUDRA_REG	0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* Right(odd TDM Slot) User Data Register File */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define DAVINCI_MCASP_DITUDRB_REG	0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* Serializer n Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define DAVINCI_MCASP_XRSRCTL_BASE_REG	0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define DAVINCI_MCASP_XRSRCTL_REG(n)	(DAVINCI_MCASP_XRSRCTL_BASE_REG + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 						(n << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* Transmit Buffer for Serializer n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define DAVINCI_MCASP_TXBUF_REG(n)	(0x200 + (n << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* Receive Buffer for Serializer n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define DAVINCI_MCASP_RXBUF_REG(n)	(0x280 + (n << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* McASP FIFO Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define DAVINCI_MCASP_V2_AFIFO_BASE	(0x1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define DAVINCI_MCASP_V3_AFIFO_BASE	(0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* FIFO register offsets from AFIFO base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MCASP_WFIFOCTL_OFFSET		(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MCASP_WFIFOSTS_OFFSET		(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define MCASP_RFIFOCTL_OFFSET		(0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define MCASP_RFIFOSTS_OFFSET		(0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  *     Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MCASP_FREE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MCASP_SOFT	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  * DAVINCI_MCASP_PDOUT_REG - Pin output in GPIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * DAVINCI_MCASP_PDSET_REG - Pin input in GPIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PIN_BIT_AXR(n)	(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PIN_BIT_AMUTE	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PIN_BIT_ACLKX	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PIN_BIT_AHCLKX	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PIN_BIT_AFSX	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PIN_BIT_ACLKR	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PIN_BIT_AHCLKR	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PIN_BIT_AFSR	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DITEN	BIT(0)	/* Transmit DIT mode enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VA	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define VB	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TXROT(val)	(val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TXSEL		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TXSSZ(val)	(val<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TXPBIT(val)	(val<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TXPAD(val)	(val<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TXORD		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define FSXDLY(val)	(val<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RXROT(val)	(val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RXSEL		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RXSSZ(val)	(val<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RXPBIT(val)	(val<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RXPAD(val)	(val<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RXORD		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define FSRDLY(val)	(val<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * DAVINCI_MCASP_TXFMCTL_REG -  Transmit Frame Control Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define FSXPOL		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AFSXE		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define FSXDUR		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define FSXMOD(val)	(val<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define FSRPOL		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AFSRE		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define FSRDUR		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define FSRMOD(val)	(val<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ACLKXDIV(val)	(val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ACLKXE		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TX_ASYNC	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ACLKXPOL	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ACLKXDIV_MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ACLKRDIV(val)	(val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ACLKRE		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RX_ASYNC	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ACLKRPOL	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ACLKRDIV_MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  *     Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AHCLKXDIV(val)	(val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AHCLKXPOL	BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AHCLKXE		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AHCLKXDIV_MASK	0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  *     Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AHCLKRDIV(val)	(val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define AHCLKRPOL	BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AHCLKRE		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AHCLKRDIV_MASK	0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * DAVINCI_MCASP_XRSRCTL_BASE_REG -  Serializer Control Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MODE(val)	(val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DISMOD_3STATE	(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DISMOD_LOW	(0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DISMOD_HIGH	(0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DISMOD_VAL(x)	((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DISMOD_MASK	DISMOD_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TXSTATE		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define RXSTATE		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SRMOD_MASK	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SRMOD_INACTIVE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define LBEN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define LBORD		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define LBGENMODE(val)	(val<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TXTDMS(n)	(1<<n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define RXTDMS(n)	(1<<n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * DAVINCI_MCASP_GBLCTL_REG -  Global Control Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define RXCLKRST	BIT(0)	/* Receiver Clock Divider Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define RXHCLKRST	BIT(1)	/* Receiver High Frequency Clock Divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define RXSERCLR	BIT(2)	/* Receiver Serializer Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define RXSMRST		BIT(3)	/* Receiver State Machine Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define RXFSRST		BIT(4)	/* Frame Sync Generator Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TXCLKRST	BIT(8)	/* Transmitter Clock Divider Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TXHCLKRST	BIT(9)	/* Transmitter High Frequency Clock Divider*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TXSERCLR	BIT(10)	/* Transmit Serializer Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TXSMRST		BIT(11)	/* Transmitter State Machine Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TXFSRST		BIT(12)	/* Frame Sync Generator Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  * DAVINCI_MCASP_TXSTAT_REG - Transmitter Status Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  * DAVINCI_MCASP_RXSTAT_REG - Receiver Status Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define XRERR		BIT(8) /* Transmit/Receive error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define XRDATA		BIT(5) /* Transmit/Receive data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  * DAVINCI_MCASP_AMUTE_REG -  Mute Control Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MUTENA(val)	(val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MUTEINPOL	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MUTEINENA	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MUTEIN		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MUTER		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MUTEX		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MUTEFSR		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MUTEFSX		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MUTEBADCLKR	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MUTEBADCLKX	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MUTERXDMAERR	BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define MUTETXDMAERR	BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define RXDATADMADIS	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TXDATADMADIS	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  * DAVINCI_MCASP_EVTCTLR_REG - Receiver Interrupt Control Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ROVRN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  * DAVINCI_MCASP_EVTCTLX_REG - Transmitter Interrupt Control Register Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define XUNDRN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define FIFO_ENABLE	BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define NUMEVT_MASK	(0xFF << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define NUMEVT(x)	(((x) & 0xFF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define NUMDMA_MASK	(0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Source of High-frequency transmit/receive clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define MCASP_CLK_HCLK_AHCLK		0 /* AHCLKX/R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define MCASP_CLK_HCLK_AUXCLK		1 /* Internal functional clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* clock divider IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define MCASP_CLKDIV_AUXCLK		0 /* HCLK divider from AUXCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MCASP_CLKDIV_BCLK		1 /* BCLK divider from HCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MCASP_CLKDIV_BCLK_FS_RATIO	2 /* to set BCLK FS ration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif	/* DAVINCI_MCASP_H */