^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA SoC McASP Audio Layer for TI DAVINCI processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Multi-channel Audio Serial Port Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Nirmal Pandey <n-pandey@ti.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Suresh Rajashekara <suresh.r@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Steve Chen <schen@.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright: (C) 2009 Texas Instruments, India
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_data/davinci_asp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "edma-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "sdma-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "udma-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "davinci-mcasp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MCASP_MAX_AFIFO_DEPTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static u32 context_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DAVINCI_MCASP_TXFMCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DAVINCI_MCASP_RXFMCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DAVINCI_MCASP_TXFMT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DAVINCI_MCASP_RXFMT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DAVINCI_MCASP_ACLKXCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DAVINCI_MCASP_ACLKRCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DAVINCI_MCASP_AHCLKXCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DAVINCI_MCASP_AHCLKRCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DAVINCI_MCASP_PDIR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DAVINCI_MCASP_PFUNC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DAVINCI_MCASP_RXMASK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DAVINCI_MCASP_TXMASK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DAVINCI_MCASP_RXTDM_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DAVINCI_MCASP_TXTDM_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct davinci_mcasp_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 config_regs[ARRAY_SIZE(context_regs)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 afifo_regs[2]; /* for read/write fifo control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 *xrsr_regs; /* for serializer configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool pm_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct davinci_mcasp_ruledata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct davinci_mcasp *mcasp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int serializers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct davinci_mcasp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct snd_dmaengine_dai_dma_data dma_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 fifo_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct snd_pcm_substream *substreams[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int dai_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* McASP specific data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 tdm_mask[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 op_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 dismod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 num_serializer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 *serial_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 bclk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 irq_request[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int dma_request[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int sysclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bool bclk_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 auxclk_fs_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long pdir; /* Pin direction bitfield */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* McASP FIFO related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 txnumevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 rxnumevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool dat_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Used for comstraint setting on the second stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int max_format_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 active_serializers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct davinci_mcasp_context context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct davinci_mcasp_ruledata ruledata[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct snd_pcm_hw_constraint_list chconstr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void __iomem *reg = mcasp->base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __raw_writel(__raw_readl(reg) | val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void __iomem *reg = mcasp->base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __raw_writel((__raw_readl(reg) & ~(val)), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 val, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void __iomem *reg = mcasp->base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __raw_writel(val, mcasp->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return (u32)__raw_readl(mcasp->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mcasp_set_bits(mcasp, ctl_reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* programming GBLCTL needs to read back from GBLCTL and verfiy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* loop count is to avoid the lock-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) printk(KERN_ERR "GBLCTL write error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 bit = PIN_BIT_AMUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void mcasp_start_rx(struct davinci_mcasp *mcasp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (mcasp->rxnumevt) { /* enable FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Start clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * When ASYNC == 0 the transmit and receive sections operate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * synchronously from the transmit clock and frame sync. We need to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * sure that the TX signlas are enabled when starting reception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (mcasp_is_synchronous(mcasp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mcasp_set_clk_pdir(mcasp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Activate serializer(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Release RX state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Release Frame Sync generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (mcasp_is_synchronous(mcasp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* enable receive IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void mcasp_start_tx(struct davinci_mcasp *mcasp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (mcasp->txnumevt) { /* enable FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Start clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mcasp_set_clk_pdir(mcasp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Activate serializer(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* wait for XDATA to be cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) (cnt < 100000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mcasp_set_axr_pdir(mcasp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Release TX state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Release Frame Sync generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* enable transmit IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mcasp->streams++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mcasp_start_tx(mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mcasp_start_rx(mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* disable IRQ sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * In synchronous mode stop the TX clocks if no other stream is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mcasp_set_clk_pdir(mcasp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (mcasp->rxnumevt) { /* disable FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* disable IRQ sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * In synchronous mode keep TX clocks running if the capture stream is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * still running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (mcasp_is_synchronous(mcasp) && mcasp->streams)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) val = TXHCLKRST | TXCLKRST | TXFSRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mcasp_set_clk_pdir(mcasp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (mcasp->txnumevt) { /* disable FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) mcasp_set_axr_pdir(mcasp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mcasp->streams--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mcasp_stop_tx(mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mcasp_stop_rx(mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 handled_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (stat & XUNDRN & irq_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_warn(mcasp->dev, "Transmit buffer underflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) handled_mask |= XUNDRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) snd_pcm_stop_xrun(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!handled_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (stat & XRERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) handled_mask |= XRERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Ack the handled event only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return IRQ_RETVAL(handled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 handled_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (stat & ROVRN & irq_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_warn(mcasp->dev, "Receive buffer overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) handled_mask |= ROVRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) snd_pcm_stop_xrun(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!handled_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (stat & XRERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) handled_mask |= XRERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Ack the handled event only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return IRQ_RETVAL(handled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = davinci_mcasp_tx_irq_handler(irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret |= davinci_mcasp_rx_irq_handler(irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 data_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) bool fs_pol_rising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) bool inv_fs = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pm_runtime_get_sync(mcasp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* 1st data bit occur one ACLK cycle after the frame sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) data_delay = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case SND_SOC_DAIFMT_AC97:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* No delay after FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) data_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* configure a full-word SYNC pulse (LRCLK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* 1st data bit occur one ACLK cycle after the frame sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) data_delay = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* FS need to be inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) inv_fs = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* configure a full-word SYNC pulse (LRCLK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* No delay after FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) data_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) FSXDLY(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) FSRDLY(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* codec is clock and frame slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* BCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Frame Sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) set_bit(PIN_BIT_AFSX, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) set_bit(PIN_BIT_AFSR, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mcasp->bclk_master = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case SND_SOC_DAIFMT_CBS_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* codec is clock slave and frame master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* BCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Frame Sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) mcasp->bclk_master = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case SND_SOC_DAIFMT_CBM_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* codec is clock master and frame slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* BCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Frame Sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) set_bit(PIN_BIT_AFSX, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) set_bit(PIN_BIT_AFSR, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mcasp->bclk_master = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* codec is clock and frame master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* BCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Frame Sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mcasp->bclk_master = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) fs_pol_rising = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) fs_pol_rising = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) fs_pol_rising = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) fs_pol_rising = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (inv_fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) fs_pol_rising = !fs_pol_rising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (fs_pol_rising) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mcasp->dai_fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pm_runtime_put(mcasp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int div, bool explicit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) pm_runtime_get_sync(mcasp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) switch (div_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case MCASP_CLKDIV_BCLK: /* BCLK divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ACLKXDIV(div - 1), ACLKXDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ACLKRDIV(div - 1), ACLKRDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (explicit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mcasp->bclk_div = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case MCASP_CLKDIV_BCLK_FS_RATIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * BCLK/LRCLK ratio descries how many bit-clock cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * fit into one frame. The clock ratio is given for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * full period of data (for I2S format both left and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * right channels), so it has to be divided by number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * of tdm-slots (for I2S - divided by 2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * Instead of storing this ratio, we calculate a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * tdm_slot width by dividing the ratio by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * number of configured tdm slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) mcasp->slot_width = div / mcasp->tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (div % mcasp->tdm_slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev_warn(mcasp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) __func__, div, mcasp->tdm_slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) pm_runtime_put(mcasp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) pm_runtime_get_sync(mcasp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (dir == SND_SOC_CLOCK_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) switch (clk_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) case MCASP_CLK_HCLK_AHCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) AHCLKXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) AHCLKRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) case MCASP_CLK_HCLK_AUXCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) AHCLKXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) AHCLKRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Select AUXCLK as HCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * When AHCLK X/R is selected to be output it means that the HCLK is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * the same clock - coming via AUXCLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) mcasp->sysclk_freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) pm_runtime_put(mcasp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* All serializers must have equal number of channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int serializers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) unsigned int *list = (unsigned int *) cl->list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int slots = mcasp->tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int i, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (mcasp->tdm_mask[stream])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) slots = hweight32(mcasp->tdm_mask[stream]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) for (i = 1; i <= slots; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) list[count++] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) for (i = 2; i <= serializers; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) list[count++] = i*slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) cl->count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int rx_serializers = 0, tx_serializers = 0, ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) for (i = 0; i < mcasp->num_serializer; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (mcasp->serial_dir[i] == TX_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) tx_serializers++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) else if (mcasp->serial_dir[i] == RX_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) rx_serializers++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) tx_serializers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) rx_serializers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) unsigned int tx_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) unsigned int rx_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int slots, int slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dev_dbg(mcasp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) __func__, tx_mask, rx_mask, slots, slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_err(mcasp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) tx_mask, rx_mask, slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (slot_width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) __func__, slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mcasp->tdm_slots = slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mcasp->slot_width = slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return davinci_mcasp_set_ch_constraints(mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) int sample_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u32 fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u32 tx_rotate, rx_rotate, slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u32 mask = (1ULL << sample_width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (mcasp->slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) slot_width = mcasp->slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) else if (mcasp->max_format_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) slot_width = mcasp->max_format_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) slot_width = sample_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * TX rotation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * right aligned formats: rotate w/ slot_width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * left aligned formats: rotate w/ sample_width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * RX rotation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * right aligned formats: no rotation needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * left aligned formats: rotate w/ (slot_width - sample_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) SND_SOC_DAIFMT_RIGHT_J) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) tx_rotate = (slot_width / 4) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) rx_rotate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) tx_rotate = (sample_width / 4) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) rx_rotate = (slot_width - sample_width) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* mapping of the XSSZ bit-field as described in the datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) fmt = (slot_width >> 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) RXSSZ(0x0F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) TXSSZ(0x0F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) TXROT(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) RXROT(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int period_words, int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u8 tx_ser = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u8 rx_ser = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u8 slots = mcasp->tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u8 max_active_serializers = (channels + slots - 1) / slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u8 max_rx_serializers, max_tx_serializers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) int active_serializers, numevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* Default configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (mcasp->version < MCASP_VERSION_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) max_tx_serializers = max_active_serializers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) max_rx_serializers =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) max_tx_serializers =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) max_rx_serializers = max_active_serializers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) for (i = 0; i < mcasp->num_serializer; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) mcasp->serial_dir[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (mcasp->serial_dir[i] == TX_MODE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) tx_ser < max_tx_serializers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) mcasp->dismod, DISMOD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) tx_ser++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) } else if (mcasp->serial_dir[i] == RX_MODE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) rx_ser < max_rx_serializers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) rx_ser++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* Inactive or unused pin, set it to inactive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) SRMOD_INACTIVE, SRMOD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* If unused, set DISMOD for the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (mcasp->serial_dir[i] != INACTIVE_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) mcasp_mod_bits(mcasp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) DAVINCI_MCASP_XRSRCTL_REG(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) mcasp->dismod, DISMOD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) active_serializers = tx_ser;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) numevt = mcasp->txnumevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) active_serializers = rx_ser;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) numevt = mcasp->rxnumevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (active_serializers < max_active_serializers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev_warn(mcasp->dev, "stream has more channels (%d) than are "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) "enabled in mcasp (%d)\n", channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) active_serializers * slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* AFIFO is not in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (!numevt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Configure the burst size for platform drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (active_serializers > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * If more than one serializers are in use we have one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * DMA request to provide data for all serializers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * For example if three serializers are enabled the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * need to transfer three words per DMA request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dma_data->maxburst = active_serializers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dma_data->maxburst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (period_words % active_serializers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dev_err(mcasp->dev, "Invalid combination of period words and "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) "active serializers: %d, %d\n", period_words,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) active_serializers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * Calculate the optimal AFIFO depth for platform side:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * The number of words for numevt need to be in steps of active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * serializers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) numevt = (numevt / active_serializers) * active_serializers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) while (period_words % numevt && numevt > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) numevt -= active_serializers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (numevt <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) numevt = active_serializers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* Configure the burst size for platform drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (numevt == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) numevt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) dma_data->maxburst = numevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) mcasp->active_serializers[stream] = active_serializers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) int i, active_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) int total_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) int active_serializers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u32 busel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) total_slots = mcasp->tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * If more than one serializer is needed, then use them with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * all the specified tdm_slots. Otherwise, one serializer can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * cope with the transaction using just as many slots as there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * are channels in the stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (mcasp->tdm_mask[stream]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) active_slots = hweight32(mcasp->tdm_mask[stream]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) active_serializers = (channels + active_slots - 1) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) active_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (active_serializers == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) active_slots = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) for (i = 0; i < total_slots; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if ((1 << i) & mcasp->tdm_mask[stream]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) mask |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (--active_slots <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) active_serializers = (channels + total_slots - 1) / total_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (active_serializers == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) active_slots = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) active_slots = total_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) for (i = 0; i < active_slots; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) mask |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (!mcasp->dat_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) busel = TXSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) FSXMOD(total_slots), FSXMOD(0x1FF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) FSRMOD(total_slots), FSRMOD(0x1FF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * If McASP is set to be TX/RX synchronous and the playback is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * not running already we need to configure the TX slots in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * order to have correct FSX on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) FSXMOD(total_slots), FSXMOD(0x1FF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* S/PDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) u32 cs_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) u8 *cs_bytes = (u8*) &cs_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) and LSB first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* Set the TX tdm : for all the slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* Set the TX clock controls : div = 1 and internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* Only 44100 and 48000 are valid, both have the same setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* Enable the DIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* Set S/PDIF channel status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) case 24000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) case 176400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) unsigned int sysclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) unsigned int bclk_freq, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) int div = sysclk_freq / bclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) int rem = sysclk_freq % bclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) int error_ppm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) int aux_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (div > (ACLKXDIV_MASK + 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (reg & AHCLKXE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) aux_div = div / (ACLKXDIV_MASK + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (div % (ACLKXDIV_MASK + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) aux_div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) sysclk_freq /= aux_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) div = sysclk_freq / bclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) rem = sysclk_freq % bclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) } else if (set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) sysclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (rem != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (div == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ((sysclk_freq / div) - bclk_freq) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) (bclk_freq - (sysclk_freq / (div+1)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) rem = rem - bclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) (int)bclk_freq)) / div - 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (error_ppm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) error_ppm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (reg & AHCLKXE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) aux_div, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return error_ppm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (!mcasp->txnumevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (!mcasp->rxnumevt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static snd_pcm_sframes_t davinci_mcasp_delay(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u32 fifo_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) fifo_use = davinci_mcasp_tx_delay(mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) fifo_use = davinci_mcasp_rx_delay(mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * Divide the used locations with the channel count to get the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * FIFO usage in samples (don't care about partial samples in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * buffer).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return fifo_use / substream->runtime->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) int word_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) int channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) int period_size = params_period_size(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) case SNDRV_PCM_FORMAT_U8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) case SNDRV_PCM_FORMAT_S8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) word_length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) case SNDRV_PCM_FORMAT_U16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) word_length = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) case SNDRV_PCM_FORMAT_U24_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) case SNDRV_PCM_FORMAT_S24_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) word_length = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) case SNDRV_PCM_FORMAT_U24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) word_length = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) case SNDRV_PCM_FORMAT_U32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) word_length = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * If mcasp is BCLK master, and a BCLK divider was not provided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * the machine driver, we need to calculate the ratio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) int slots = mcasp->tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) int sbits = params_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (mcasp->slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) sbits = mcasp->slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) rate * sbits * slots, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ret = mcasp_common_hw_param(mcasp, substream->stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) period_size * channels, channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ret = mcasp_dit_hw_param(mcasp, params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret = mcasp_i2s_hw_param(mcasp, substream->stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) davinci_config_channel_size(mcasp, word_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) mcasp->channels = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (!mcasp->max_format_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) mcasp->max_format_width = word_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) int cmd, struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) davinci_mcasp_start(mcasp, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) davinci_mcasp_stop(mcasp, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct snd_pcm_hw_rule *rule)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) struct davinci_mcasp_ruledata *rd = rule->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct snd_mask nfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) int i, slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) snd_mask_none(&nfmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) slot_width = rd->mcasp->slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (snd_mask_test(fmt, i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (snd_pcm_format_width(i) <= slot_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) snd_mask_set(&nfmt, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) return snd_mask_refine(fmt, &nfmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct snd_pcm_hw_rule *rule)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct davinci_mcasp_ruledata *rd = rule->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct snd_mask nfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) int i, format_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) snd_mask_none(&nfmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) format_width = rd->mcasp->max_format_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (snd_mask_test(fmt, i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (snd_pcm_format_width(i) == format_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) snd_mask_set(&nfmt, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) return snd_mask_refine(fmt, &nfmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static const unsigned int davinci_mcasp_dai_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) 88200, 96000, 176400, 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define DAVINCI_MAX_RATE_ERROR_PPM 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct snd_pcm_hw_rule *rule)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) struct davinci_mcasp_ruledata *rd = rule->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct snd_interval *ri =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) int sbits = params_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) int slots = rd->mcasp->tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct snd_interval range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (rd->mcasp->slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) sbits = rd->mcasp->slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) snd_interval_any(&range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) range.empty = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) uint bclk_freq = sbits * slots *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) davinci_mcasp_dai_rates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) unsigned int sysclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) int ppm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (rd->mcasp->auxclk_fs_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) sysclk_freq = davinci_mcasp_dai_rates[i] *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) rd->mcasp->auxclk_fs_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) sysclk_freq = rd->mcasp->sysclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) bclk_freq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (range.empty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) range.min = davinci_mcasp_dai_rates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) range.empty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) range.max = davinci_mcasp_dai_rates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) dev_dbg(rd->mcasp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ri->min, ri->max, range.min, range.max, sbits, slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return snd_interval_refine(hw_param_interval(params, rule->var),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) &range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct snd_pcm_hw_rule *rule)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct davinci_mcasp_ruledata *rd = rule->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) struct snd_mask nfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) int slots = rd->mcasp->tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) int i, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) snd_mask_none(&nfmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (snd_mask_test(fmt, i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) uint sbits = snd_pcm_format_width(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) unsigned int sysclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) int ppm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (rd->mcasp->auxclk_fs_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) sysclk_freq = rate *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) rd->mcasp->auxclk_fs_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) sysclk_freq = rd->mcasp->sysclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (rd->mcasp->slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) sbits = rd->mcasp->slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) sbits * slots * rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) snd_mask_set(&nfmt, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) dev_dbg(rd->mcasp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) "%d possible sample format for %d Hz and %d tdm slots\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) count, rate, slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return snd_mask_refine(fmt, &nfmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static int davinci_mcasp_hw_rule_min_periodsize(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) struct snd_interval *period_size = hw_param_interval(params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) struct snd_interval frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) snd_interval_any(&frames);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) frames.min = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) frames.integer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return snd_interval_refine(period_size, &frames);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) struct davinci_mcasp_ruledata *ruledata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) &mcasp->ruledata[substream->stream];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) u32 max_channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) int i, dir, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) int tdm_slots = mcasp->tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* Do not allow more then one stream per direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (mcasp->substreams[substream->stream])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) mcasp->substreams[substream->stream] = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (mcasp->tdm_mask[substream->stream])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) * Limit the maximum allowed channels for the first stream:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) * number of serializers for the direction * tdm slots per serializer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) dir = TX_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) dir = RX_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) for (i = 0; i < mcasp->num_serializer; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (mcasp->serial_dir[i] == dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) max_channels++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) ruledata->serializers = max_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) ruledata->mcasp = mcasp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) max_channels *= tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) * If the already active stream has less channels than the calculated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) * limit based on the seirializers * tdm_slots, and only one serializer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) * is in use we need to use that as a constraint for the second stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * Otherwise (first stream or less allowed channels or more than one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) * serializer in use) we use the calculated constraint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (mcasp->channels && mcasp->channels < max_channels &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) ruledata->serializers == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) max_channels = mcasp->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * But we can always allow channels upto the amount of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * the available tdm_slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (max_channels < tdm_slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) max_channels = tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) snd_pcm_hw_constraint_minmax(substream->runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) SNDRV_PCM_HW_PARAM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) 0, max_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) snd_pcm_hw_constraint_list(substream->runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) 0, SNDRV_PCM_HW_PARAM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) &mcasp->chconstr[substream->stream]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (mcasp->max_format_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) * Only allow formats which require same amount of bits on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * bus as the currently running stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) ret = snd_pcm_hw_rule_add(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) SNDRV_PCM_HW_PARAM_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) davinci_mcasp_hw_rule_format_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) ruledata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) SNDRV_PCM_HW_PARAM_FORMAT, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) else if (mcasp->slot_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /* Only allow formats require <= slot_width bits on the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) ret = snd_pcm_hw_rule_add(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) SNDRV_PCM_HW_PARAM_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) davinci_mcasp_hw_rule_slot_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) ruledata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) SNDRV_PCM_HW_PARAM_FORMAT, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * If we rely on implicit BCLK divider setting we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * set constraints based on what we can provide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) ret = snd_pcm_hw_rule_add(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) davinci_mcasp_hw_rule_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) ruledata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) SNDRV_PCM_HW_PARAM_FORMAT, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) ret = snd_pcm_hw_rule_add(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) SNDRV_PCM_HW_PARAM_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) davinci_mcasp_hw_rule_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ruledata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) SNDRV_PCM_HW_PARAM_RATE, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) snd_pcm_hw_rule_add(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) davinci_mcasp_hw_rule_min_periodsize, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) mcasp->substreams[substream->stream] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) mcasp->active_serializers[substream->stream] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) if (!snd_soc_dai_active(cpu_dai)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) mcasp->channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) mcasp->max_format_width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .startup = davinci_mcasp_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .shutdown = davinci_mcasp_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .trigger = davinci_mcasp_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .delay = davinci_mcasp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .hw_params = davinci_mcasp_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .set_fmt = davinci_mcasp_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .set_clkdiv = davinci_mcasp_set_clkdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .set_sysclk = davinci_mcasp_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .set_tdm_slot = davinci_mcasp_set_tdm_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) SNDRV_PCM_FMTBIT_U8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) SNDRV_PCM_FMTBIT_U16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) SNDRV_PCM_FMTBIT_S24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) SNDRV_PCM_FMTBIT_U24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) SNDRV_PCM_FMTBIT_S24_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) SNDRV_PCM_FMTBIT_U24_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) SNDRV_PCM_FMTBIT_S32_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) SNDRV_PCM_FMTBIT_U32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .name = "davinci-mcasp.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .probe = davinci_mcasp_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .stream_name = "IIS Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .channels_max = 32 * 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .rates = DAVINCI_MCASP_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .formats = DAVINCI_MCASP_PCM_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .stream_name = "IIS Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .channels_max = 32 * 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .rates = DAVINCI_MCASP_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .formats = DAVINCI_MCASP_PCM_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .ops = &davinci_mcasp_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .name = "davinci-mcasp.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .probe = davinci_mcasp_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .stream_name = "DIT Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .channels_max = 384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .rates = DAVINCI_MCASP_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .formats = DAVINCI_MCASP_PCM_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .ops = &davinci_mcasp_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) static const struct snd_soc_component_driver davinci_mcasp_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .name = "davinci-mcasp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) /* Some HW specific values and defaults. The rest is filled in from DT. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .tx_dma_offset = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .rx_dma_offset = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .version = MCASP_VERSION_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) static struct davinci_mcasp_pdata da830_mcasp_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .tx_dma_offset = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .rx_dma_offset = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .version = MCASP_VERSION_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .tx_dma_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .rx_dma_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .version = MCASP_VERSION_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) /* The CFG port offset will be calculated if it is needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .tx_dma_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .rx_dma_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .version = MCASP_VERSION_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) static const struct of_device_id mcasp_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .compatible = "ti,dm646x-mcasp-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .data = &dm646x_mcasp_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .compatible = "ti,da830-mcasp-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .data = &da830_mcasp_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .compatible = "ti,am33xx-mcasp-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .data = &am33xx_mcasp_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .compatible = "ti,dra7-mcasp-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .data = &dra7_mcasp_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) static int mcasp_reparent_fck(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) struct clk *gfclk, *parent_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) parent_name = of_get_property(node, "fck_parent", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (!parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) gfclk = clk_get(&pdev->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (IS_ERR(gfclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) dev_err(&pdev->dev, "failed to get fck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) return PTR_ERR(gfclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) parent_clk = clk_get(NULL, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (IS_ERR(parent_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) dev_err(&pdev->dev, "failed to get parent clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) ret = PTR_ERR(parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) ret = clk_set_parent(gfclk, parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) dev_err(&pdev->dev, "failed to reparent fck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) clk_put(parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) clk_put(gfclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) struct davinci_mcasp_pdata *pdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) const struct of_device_id *match =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) of_match_device(mcasp_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) struct of_phandle_args dma_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) const u32 *of_serial_dir32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if (pdev->dev.platform_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) pdata->dismod = DISMOD_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) } else if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) /* control shouldn't reach here. something is wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) goto nodata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) ret = of_property_read_u32(np, "op-mode", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) pdata->op_mode = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) ret = of_property_read_u32(np, "tdm-slots", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if (val < 2 || val > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) "tdm-slots must be in rage [2-32]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) goto nodata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) pdata->tdm_slots = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) of_serial_dir32 = of_get_property(np, "serial-dir", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) val /= sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (of_serial_dir32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) (sizeof(*of_serial_dir) * val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (!of_serial_dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) goto nodata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) for (i = 0; i < val; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) pdata->num_serializer = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) pdata->serial_dir = of_serial_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ret = of_property_match_string(np, "dma-names", "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) goto nodata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) &dma_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) goto nodata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) pdata->tx_dma_channel = dma_spec.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) /* RX is not valid in DIT mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) ret = of_property_match_string(np, "dma-names", "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) goto nodata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) &dma_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) goto nodata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) pdata->rx_dma_channel = dma_spec.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) ret = of_property_read_u32(np, "tx-num-evt", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) pdata->txnumevt = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ret = of_property_read_u32(np, "rx-num-evt", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) pdata->rxnumevt = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) ret = of_property_read_u32(np, "sram-size-playback", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) pdata->sram_size_playback = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) ret = of_property_read_u32(np, "sram-size-capture", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) pdata->sram_size_capture = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) ret = of_property_read_u32(np, "dismod", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (val == 0 || val == 2 || val == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) pdata->dismod = DISMOD_VAL(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) pdata->dismod = DISMOD_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) pdata->dismod = DISMOD_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) nodata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) dev_err(&pdev->dev, "Error populating platform data, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) pdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) PCM_EDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) PCM_SDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) PCM_UDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static const char *sdma_prefix = "ti,omap";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) const char *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) int ret = PCM_EDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (!mcasp->dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return PCM_EDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) chan = dma_request_chan(mcasp->dev, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if (IS_ERR(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (PTR_ERR(chan) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) dev_err(mcasp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) "Can't verify DMA configuration (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) PTR_ERR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) return PTR_ERR(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) if (WARN_ON(!chan->device || !chan->device->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) dma_release_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (chan->device->dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) ret = of_property_read_string(chan->device->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) "compatible", &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) dma_release_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) return PCM_SDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) else if (strstr(tmp, "udmap"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) return PCM_UDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) return PCM_EDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) u32 offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if (pdata->version != MCASP_VERSION_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) return pdata->tx_dma_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) for (i = 0; i < pdata->num_serializer; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (pdata->serial_dir[i] == TX_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) if (!offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) offset = DAVINCI_MCASP_TXBUF_REG(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) pr_err("%s: Only one serializer allowed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) u32 offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if (pdata->version != MCASP_VERSION_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) return pdata->rx_dma_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) for (i = 0; i < pdata->num_serializer; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (pdata->serial_dir[i] == RX_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) if (!offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) offset = DAVINCI_MCASP_RXBUF_REG(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) pr_err("%s: Only one serializer allowed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if (mcasp->num_serializer && offset < mcasp->num_serializer &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) mcasp->serial_dir[offset] != INACTIVE_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) /* Do not change the PIN yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) return pm_runtime_get_sync(mcasp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) /* Set the direction to input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) /* Set the pin as McASP pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) pm_runtime_put_sync(mcasp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) if (!(val & BIT(offset))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) /* Set the pin as GPIO pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) /* Set the direction to output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) if (!(val & BIT(offset))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) /* Set the direction to input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) /* Set the pin as GPIO pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) if (val & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if (val & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) static const struct gpio_chip davinci_mcasp_template_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .request = davinci_mcasp_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .free = davinci_mcasp_gpio_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .direction_output = davinci_mcasp_gpio_direction_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .set = davinci_mcasp_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .direction_input = davinci_mcasp_gpio_direction_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .get = davinci_mcasp_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .get_direction = davinci_mcasp_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .ngpio = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) mcasp->gpio_chip = davinci_mcasp_template_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) mcasp->gpio_chip.label = dev_name(mcasp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) mcasp->gpio_chip.parent = mcasp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) #ifdef CONFIG_OF_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) mcasp->gpio_chip.of_node = mcasp->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) #else /* CONFIG_GPIOLIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) #endif /* CONFIG_GPIOLIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) static int davinci_mcasp_get_dt_params(struct davinci_mcasp *mcasp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) struct device_node *np = mcasp->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) ret = of_property_read_u32(np, "auxclk-fs-ratio", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) mcasp->auxclk_fs_ratio = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) static int davinci_mcasp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) struct snd_dmaengine_dai_dma_data *dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) struct resource *mem, *res, *dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) struct davinci_mcasp_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) struct davinci_mcasp *mcasp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) char *irq_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) int *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (!pdev->dev.platform_data && !pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) dev_err(&pdev->dev, "No platform data supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (!mcasp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) pdata = davinci_mcasp_set_pdata_from_of(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) dev_err(&pdev->dev, "no platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) if (!mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) "\"mpu\" mem resource not found, using index 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (!mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) dev_err(&pdev->dev, "no mem resource?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) if (IS_ERR(mcasp->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) return PTR_ERR(mcasp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) mcasp->op_mode = pdata->op_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) /* sanity check for tdm slots parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) if (pdata->tdm_slots < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) dev_err(&pdev->dev, "invalid tdm slots: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) pdata->tdm_slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) mcasp->tdm_slots = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) } else if (pdata->tdm_slots > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) dev_err(&pdev->dev, "invalid tdm slots: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) pdata->tdm_slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) mcasp->tdm_slots = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) mcasp->tdm_slots = pdata->tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) mcasp->num_serializer = pdata->num_serializer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) mcasp->num_serializer, sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) if (!mcasp->context.xrsr_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) mcasp->serial_dir = pdata->serial_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) mcasp->version = pdata->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) mcasp->txnumevt = pdata->txnumevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) mcasp->rxnumevt = pdata->rxnumevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) mcasp->dismod = pdata->dismod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) mcasp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) irq = platform_get_irq_byname(pdev, "common");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) if (irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) if (!irq_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) davinci_mcasp_common_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) IRQF_ONESHOT | IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) irq_name, mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) dev_err(&pdev->dev, "common IRQ request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) irq = platform_get_irq_byname(pdev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) if (irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) if (!irq_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) davinci_mcasp_rx_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) IRQF_ONESHOT, irq_name, mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) dev_err(&pdev->dev, "RX IRQ request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) irq = platform_get_irq_byname(pdev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) if (irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) if (!irq_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) davinci_mcasp_tx_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) IRQF_ONESHOT, irq_name, mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) dev_err(&pdev->dev, "TX IRQ request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) if (dat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) mcasp->dat_port = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) if (dat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) dma_data->addr = dat->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) *dma = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) *dma = pdata->tx_dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) /* dmaengine filter data for DT and non-DT boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) dma_data->filter_data = "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) dma_data->filter_data = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) /* RX is not valid in DIT mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if (dat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) dma_data->addr = dat->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) dma_data->addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) mem->start + davinci_mcasp_rxdma_offset(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) *dma = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) *dma = pdata->rx_dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) /* dmaengine filter data for DT and non-DT boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) dma_data->filter_data = "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) dma_data->filter_data = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) if (mcasp->version < MCASP_VERSION_3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) /* dma_params->dma_addr is pointing to the data port address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) mcasp->dat_port = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) /* Allocate memory for long enough list for all possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) * scenarios. Maximum number tdm slots is 32 and there cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) * be more serializers than given in the configuration. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) * serializer directions could be taken into account, but it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) * would make code much more complex and save only couple of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) * bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) devm_kcalloc(mcasp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) 32 + mcasp->num_serializer - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) sizeof(unsigned int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) devm_kcalloc(mcasp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) 32 + mcasp->num_serializer - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) sizeof(unsigned int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) ret = davinci_mcasp_set_ch_constraints(mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) dev_set_drvdata(&pdev->dev, mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) mcasp_reparent_fck(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) /* All PINS as McASP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) pm_runtime_get_sync(mcasp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) pm_runtime_put(mcasp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) ret = davinci_mcasp_init_gpiochip(mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) ret = davinci_mcasp_get_dt_params(mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) &davinci_mcasp_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) &davinci_mcasp_dai[pdata->op_mode], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) ret = davinci_mcasp_get_dma_type(mcasp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) switch (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) case PCM_EDMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) ret = edma_pcm_platform_register(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) case PCM_SDMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) case PCM_UDMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) ret = udma_pcm_platform_register(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) case -EPROBE_DEFER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) static int davinci_mcasp_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) static int davinci_mcasp_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) struct davinci_mcasp_context *context = &mcasp->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) for (i = 0; i < ARRAY_SIZE(context_regs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) if (mcasp->txnumevt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) if (mcasp->rxnumevt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) for (i = 0; i < mcasp->num_serializer; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) context->xrsr_regs[i] = mcasp_get_reg(mcasp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) DAVINCI_MCASP_XRSRCTL_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) static int davinci_mcasp_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) struct davinci_mcasp_context *context = &mcasp->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) for (i = 0; i < ARRAY_SIZE(context_regs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) if (mcasp->txnumevt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) if (mcasp->rxnumevt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) for (i = 0; i < mcasp->num_serializer; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) context->xrsr_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) static const struct dev_pm_ops davinci_mcasp_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) davinci_mcasp_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) static struct platform_driver davinci_mcasp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .probe = davinci_mcasp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .remove = davinci_mcasp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .name = "davinci-mcasp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .pm = &davinci_mcasp_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .of_match_table = mcasp_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) module_platform_driver(davinci_mcasp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) MODULE_AUTHOR("Steve Chen");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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