^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tegra30_i2s.h - Definitions for Tegra30 I2S driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __TEGRA30_I2S_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __TEGRA30_I2S_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "tegra_pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Register offsets from TEGRA30_I2S*_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA30_I2S_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA30_I2S_TIMING 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA30_I2S_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA30_I2S_CH_CTRL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA30_I2S_SLOT_CTRL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA30_I2S_CIF_RX_CTRL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA30_I2S_CIF_TX_CTRL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA30_I2S_FLOWCTL 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA30_I2S_TX_STEP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA30_I2S_FLOW_STATUS 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA30_I2S_FLOW_TOTAL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA30_I2S_FLOW_OVER 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA30_I2S_FLOW_UNDER 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA30_I2S_LCOEF_1_4_0 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA30_I2S_LCOEF_1_4_1 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA30_I2S_LCOEF_1_4_2 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA30_I2S_LCOEF_1_4_3 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA30_I2S_LCOEF_1_4_4 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA30_I2S_LCOEF_1_4_5 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA30_I2S_LCOEF_2_4_0 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA30_I2S_LCOEF_2_4_1 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA30_I2S_LCOEF_2_4_2 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Fields in TEGRA30_I2S_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA30_I2S_CTRL_XFER_EN_TX (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA30_I2S_CTRL_XFER_EN_RX (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA30_I2S_CTRL_CG_EN (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA30_I2S_CTRL_SOFT_RESET (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA30_I2S_CTRL_TX_FLOWCTL_EN (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA30_I2S_CTRL_OBS_SEL_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA30_I2S_CTRL_OBS_SEL_MASK (7 << TEGRA30_I2S_CTRL_OBS_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA30_I2S_FRAME_FORMAT_LRCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEGRA30_I2S_FRAME_FORMAT_FSYNC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK (7 << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK (TEGRA30_I2S_FRAME_FORMAT_LRCK << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC (TEGRA30_I2S_FRAME_FORMAT_FSYNC << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TEGRA30_I2S_CTRL_MASTER_ENABLE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEGRA30_I2S_LRCK_LEFT_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TEGRA30_I2S_LRCK_RIGHT_LOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA30_I2S_CTRL_LRCK_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TEGRA30_I2S_CTRL_LRCK_MASK (1 << TEGRA30_I2S_CTRL_LRCK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA30_I2S_CTRL_LRCK_L_LOW (TEGRA30_I2S_LRCK_LEFT_LOW << TEGRA30_I2S_CTRL_LRCK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA30_I2S_CTRL_LRCK_R_LOW (TEGRA30_I2S_LRCK_RIGHT_LOW << TEGRA30_I2S_CTRL_LRCK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA30_I2S_CTRL_LPBK_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA30_I2S_BIT_CODE_LINEAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA30_I2S_BIT_CODE_ULAW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TEGRA30_I2S_BIT_CODE_ALAW 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA30_I2S_CTRL_BIT_CODE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEGRA30_I2S_CTRL_BIT_CODE_MASK (3 << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TEGRA30_I2S_CTRL_BIT_CODE_LINEAR (TEGRA30_I2S_BIT_CODE_LINEAR << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEGRA30_I2S_CTRL_BIT_CODE_ULAW (TEGRA30_I2S_BIT_CODE_ULAW << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TEGRA30_I2S_CTRL_BIT_CODE_ALAW (TEGRA30_I2S_BIT_CODE_ALAW << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TEGRA30_I2S_BITS_8 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TEGRA30_I2S_BITS_12 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TEGRA30_I2S_BITS_16 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TEGRA30_I2S_BITS_20 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TEGRA30_I2S_BITS_24 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TEGRA30_I2S_BITS_28 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TEGRA30_I2S_BITS_32 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TEGRA30_I2S_CTRL_BIT_SIZE_MASK (7 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TEGRA30_I2S_CTRL_BIT_SIZE_8 (TEGRA30_I2S_BITS_8 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TEGRA30_I2S_CTRL_BIT_SIZE_12 (TEGRA30_I2S_BITS_12 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TEGRA30_I2S_CTRL_BIT_SIZE_16 (TEGRA30_I2S_BITS_16 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TEGRA30_I2S_CTRL_BIT_SIZE_20 (TEGRA30_I2S_BITS_20 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TEGRA30_I2S_CTRL_BIT_SIZE_24 (TEGRA30_I2S_BITS_24 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TEGRA30_I2S_CTRL_BIT_SIZE_28 (TEGRA30_I2S_BITS_28 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TEGRA30_I2S_CTRL_BIT_SIZE_32 (TEGRA30_I2S_BITS_32 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Fields in TEGRA30_I2S_TIMING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA30_I2S_TIMING_NON_SYM_ENABLE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK (TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Fields in TEGRA30_I2S_OFFSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK (TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK (TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Fields in TEGRA30_I2S_CH_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* (FSYNC width - 1) in bit clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK (TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US << TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TEGRA30_I2S_HIGHZ_NO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA30_I2S_HIGHZ_YES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_MASK (3 << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_NO (TEGRA30_I2S_HIGHZ_NO << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_YES (TEGRA30_I2S_HIGHZ_YES << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK (TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA30_I2S_MSB_FIRST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA30_I2S_LSB_FIRST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MASK (1 << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST (TEGRA30_I2S_MSB_FIRST << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST (TEGRA30_I2S_LSB_FIRST << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MASK (1 << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST (TEGRA30_I2S_MSB_FIRST << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST (TEGRA30_I2S_LSB_FIRST << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TEGRA30_I2S_POS_EDGE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA30_I2S_NEG_EDGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK (1 << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE (TEGRA30_I2S_POS_EDGE << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE (TEGRA30_I2S_NEG_EDGE << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Sample size is # bits from BIT_SIZE minus this field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK (TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US << TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK (TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US << TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Fields in TEGRA30_I2S_SLOT_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Number of slots in frame, minus 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK (TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* TDM mode slot enable bitmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK (0xff << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK (0xff << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Fields in TEGRA30_I2S_CIF_RX_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Fields in TEGRA30_I2S_CIF_TX_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Fields in TEGRA30_I2S_FLOWCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TEGRA30_I2S_FILTER_LINEAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TEGRA30_I2S_FILTER_QUAD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TEGRA30_I2S_FLOWCTL_FILTER_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TEGRA30_I2S_FLOWCTL_FILTER_MASK (1 << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TEGRA30_I2S_FLOWCTL_FILTER_LINEAR (TEGRA30_I2S_FILTER_LINEAR << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TEGRA30_I2S_FLOWCTL_FILTER_QUAD (TEGRA30_I2S_FILTER_QUAD << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Fields in TEGRA30_I2S_TX_STEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEGRA30_I2S_TX_STEP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TEGRA30_I2S_TX_STEP_MASK_US 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TEGRA30_I2S_TX_STEP_MASK (TEGRA30_I2S_TX_STEP_MASK_US << TEGRA30_I2S_TX_STEP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Fields in TEGRA30_I2S_FLOW_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TEGRA30_I2S_FLOW_STATUS_UNDERFLOW (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TEGRA30_I2S_FLOW_STATUS_OVERFLOW (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TEGRA30_I2S_FLOW_STATUS_MONITOR_INT_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TEGRA30_I2S_FLOW_STATUS_COUNTER_CLR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TEGRA30_I2S_FLOW_STATUS_MONITOR_CLR (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TEGRA30_I2S_FLOW_STATUS_COUNTER_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TEGRA30_I2S_FLOW_STATUS_MONITOR_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * There are no fields in TEGRA30_I2S_FLOW_TOTAL, TEGRA30_I2S_FLOW_OVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * TEGRA30_I2S_FLOW_UNDER; they are counters taking the whole register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Fields in TEGRA30_I2S_LCOEF_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TEGRA30_I2S_LCOEF_COEF_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TEGRA30_I2S_LCOEF_COEF_MASK_US 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TEGRA30_I2S_LCOEF_COEF_MASK (TEGRA30_I2S_LCOEF_COEF_MASK_US << TEGRA30_I2S_LCOEF_COEF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct tegra30_i2s_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void (*set_audio_cif)(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct tegra30_ahub_cif_conf *conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct tegra30_i2s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) const struct tegra30_i2s_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct snd_soc_dai_driver dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int cif_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct clk *clk_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) enum tegra30_ahub_txcif capture_i2s_cif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) enum tegra30_ahub_rxcif capture_fifo_cif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) char capture_dma_chan[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct snd_dmaengine_dai_dma_data capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) enum tegra30_ahub_rxcif playback_i2s_cif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) enum tegra30_ahub_txcif playback_fifo_cif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) char playback_dma_chan[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct snd_dmaengine_dai_dma_data playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct snd_dmaengine_pcm_config dma_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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