^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tegra30_i2s.c - Tegra30 I2S driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Stephen Warren <swarren@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on code copyright/by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) 2009-2010, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Scott Peterson <speterson@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2010 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Iliyan Malchev <malchev@google.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "tegra30_ahub.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "tegra30_i2s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRV_NAME "tegra30-i2s"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int tegra30_i2s_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct tegra30_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) regcache_cache_only(i2s->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) clk_disable_unprepare(i2s->clk_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int tegra30_i2s_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct tegra30_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ret = clk_prepare_enable(i2s->clk_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dev_err(dev, "clk_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) regcache_cache_only(i2s->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int mask = 0, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mask |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) val |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) TEGRA30_I2S_CTRL_LRCK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pm_runtime_get_sync(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pm_runtime_put(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct device *dev = dai->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int mask, val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int ret, sample_size, srate, i2sclock, bitcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct tegra30_ahub_cif_conf cif_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (params_channels(params) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) sample_size = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) srate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Final "* 2" required by Tegra hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) i2sclock = srate * params_channels(params) * sample_size * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bitcnt = (i2sclock / (2 * srate)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = clk_set_rate(i2s->clk_i2s, i2sclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (i2sclock % (2 * srate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) cif_conf.threshold = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) cif_conf.audio_channels = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) cif_conf.client_channels = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) cif_conf.expand = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cif_conf.stereo_conv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) cif_conf.replicate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) cif_conf.truncate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cif_conf.mono_conv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) reg = TEGRA30_I2S_CIF_RX_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) reg = TEGRA30_I2S_CIF_TX_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) TEGRA30_I2S_CTRL_XFER_EN_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) TEGRA30_I2S_CTRL_XFER_EN_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) TEGRA30_I2S_CTRL_XFER_EN_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) TEGRA30_I2S_CTRL_XFER_EN_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) tegra30_i2s_start_playback(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) tegra30_i2s_start_capture(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) tegra30_i2s_stop_playback(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) tegra30_i2s_stop_capture(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int tegra30_i2s_set_tdm(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int tx_mask, unsigned int rx_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int slots, int slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev_dbg(dai->dev, "%s: txmask=0x%08x rxmask=0x%08x slots=%d width=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) __func__, tx_mask, rx_mask, slots, slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mask = TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) val = (tx_mask << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) (rx_mask << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ((slots - 1) << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pm_runtime_get_sync(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) regmap_update_bits(i2s->regmap, TEGRA30_I2S_SLOT_CTRL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* set the fsync width to minimum of 1 clock width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) regmap_update_bits(i2s->regmap, TEGRA30_I2S_CH_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pm_runtime_put(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int tegra30_i2s_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dai->capture_dma_data = &i2s->capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dai->playback_dma_data = &i2s->playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .set_fmt = tegra30_i2s_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .hw_params = tegra30_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .trigger = tegra30_i2s_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .set_tdm_slot = tegra30_i2s_set_tdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .probe = tegra30_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .stream_name = "Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .rates = SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .stream_name = "Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .rates = SNDRV_PCM_RATE_8000_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .ops = &tegra30_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct snd_soc_component_driver tegra30_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case TEGRA30_I2S_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case TEGRA30_I2S_TIMING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case TEGRA30_I2S_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case TEGRA30_I2S_CH_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case TEGRA30_I2S_SLOT_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case TEGRA30_I2S_CIF_RX_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case TEGRA30_I2S_CIF_TX_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case TEGRA30_I2S_FLOWCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case TEGRA30_I2S_TX_STEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case TEGRA30_I2S_FLOW_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case TEGRA30_I2S_FLOW_TOTAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case TEGRA30_I2S_FLOW_OVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case TEGRA30_I2S_FLOW_UNDER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case TEGRA30_I2S_LCOEF_1_4_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case TEGRA30_I2S_LCOEF_1_4_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case TEGRA30_I2S_LCOEF_1_4_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case TEGRA30_I2S_LCOEF_1_4_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case TEGRA30_I2S_LCOEF_1_4_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case TEGRA30_I2S_LCOEF_1_4_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case TEGRA30_I2S_LCOEF_2_4_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case TEGRA30_I2S_LCOEF_2_4_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case TEGRA30_I2S_LCOEF_2_4_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case TEGRA30_I2S_FLOW_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case TEGRA30_I2S_FLOW_TOTAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case TEGRA30_I2S_FLOW_OVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case TEGRA30_I2S_FLOW_UNDER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const struct regmap_config tegra30_i2s_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .max_register = TEGRA30_I2S_LCOEF_2_4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .writeable_reg = tegra30_i2s_wr_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .readable_reg = tegra30_i2s_wr_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .volatile_reg = tegra30_i2s_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct tegra30_i2s_soc_data tegra30_i2s_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .set_audio_cif = tegra30_ahub_set_cif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const struct tegra30_i2s_soc_data tegra124_i2s_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .set_audio_cif = tegra124_ahub_set_cif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct of_device_id tegra30_i2s_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int tegra30_i2s_platform_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct tegra30_i2s *i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u32 cif_ids[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!i2s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_set_drvdata(&pdev->dev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) match = of_match_device(tegra30_i2s_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_err(&pdev->dev, "Error: No device match found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) i2s->soc_data = (struct tegra30_i2s_soc_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) i2s->dai = tegra30_i2s_dai_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) i2s->dai.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = of_property_read_u32_array(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) "nvidia,ahub-cif-ids", cif_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ARRAY_SIZE(cif_ids));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) i2s->playback_i2s_cif = cif_ids[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) i2s->capture_i2s_cif = cif_ids[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) i2s->clk_i2s = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (IS_ERR(i2s->clk_i2s)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = PTR_ERR(i2s->clk_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (IS_ERR(regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) goto err_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) &tegra30_i2s_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (IS_ERR(i2s->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(&pdev->dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret = PTR_ERR(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) goto err_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) regcache_cache_only(i2s->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = tegra30_i2s_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) i2s->playback_dma_data.maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) i2s->playback_dma_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) sizeof(i2s->playback_dma_chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) &i2s->playback_dma_data.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) i2s->playback_fifo_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) goto err_free_tx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) i2s->capture_dma_data.maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) i2s->capture_dma_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sizeof(i2s->capture_dma_chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) &i2s->capture_dma_data.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto err_unroute_tx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) i2s->capture_i2s_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) goto err_free_rx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) &i2s->dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) goto err_unroute_rx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) &i2s->dma_config, i2s->playback_dma_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) i2s->capture_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) goto err_unregister_component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) err_unregister_component:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) snd_soc_unregister_component(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) err_unroute_rx_fifo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) err_free_rx_fifo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) err_unroute_tx_fifo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) err_free_tx_fifo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) err_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) tegra30_i2s_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) err_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) clk_put(i2s->clk_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int tegra30_i2s_platform_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) tegra30_i2s_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) tegra_pcm_platform_unregister(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) snd_soc_unregister_component(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) clk_put(i2s->clk_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int tegra30_i2s_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct tegra30_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) regcache_mark_dirty(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int tegra30_i2s_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct tegra30_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = regcache_sync(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static const struct dev_pm_ops tegra30_i2s_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) tegra30_i2s_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) SET_SYSTEM_SLEEP_PM_OPS(tegra30_i2s_suspend, tegra30_i2s_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static struct platform_driver tegra30_i2s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .of_match_table = tegra30_i2s_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .pm = &tegra30_i2s_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .probe = tegra30_i2s_platform_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .remove = tegra30_i2s_platform_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) module_platform_driver(tegra30_i2s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MODULE_ALIAS("platform:" DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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