^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tegra30_ahub.h - Definitions for Tegra30 AHUB driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __TEGRA30_AHUB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __TEGRA30_AHUB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Channel count minus 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Channel count minus 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Channel count minus 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Channel count minus 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA30_AUDIOCIF_BITS_4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA30_AUDIOCIF_BITS_8 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA30_AUDIOCIF_BITS_12 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA30_AUDIOCIF_BITS_16 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA30_AUDIOCIF_BITS_20 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA30_AUDIOCIF_BITS_24 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA30_AUDIOCIF_BITS_28 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA30_AUDIOCIF_BITS_32 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TEGRA30_AUDIOCIF_EXPAND_ZERO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA30_AUDIOCIF_EXPAND_ONE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEGRA30_AUDIOCIF_EXPAND_LFSR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TEGRA30_AUDIOCIF_CTRL_EXPAND_MASK (3 << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ZERO (TEGRA30_AUDIOCIF_EXPAND_ZERO << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ONE (TEGRA30_AUDIOCIF_EXPAND_ONE << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TEGRA30_AUDIOCIF_CTRL_EXPAND_LFSR (TEGRA30_AUDIOCIF_EXPAND_LFSR << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TEGRA30_AUDIOCIF_STEREO_CONV_CH0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TEGRA30_AUDIOCIF_STEREO_CONV_CH1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TEGRA30_AUDIOCIF_STEREO_CONV_AVG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK (3 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH0 (TEGRA30_AUDIOCIF_STEREO_CONV_CH0 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH1 (TEGRA30_AUDIOCIF_STEREO_CONV_CH1 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG (TEGRA30_AUDIOCIF_STEREO_CONV_AVG << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TEGRA30_AUDIOCIF_DIRECTION_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TEGRA30_AUDIOCIF_DIRECTION_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK (1 << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX (TEGRA30_AUDIOCIF_DIRECTION_TX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX (TEGRA30_AUDIOCIF_DIRECTION_RX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA30_AUDIOCIF_TRUNCATE_ROUND 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA30_AUDIOCIF_TRUNCATE_CHOP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_MASK (1 << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_ROUND (TEGRA30_AUDIOCIF_TRUNCATE_ROUND << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_CHOP (TEGRA30_AUDIOCIF_TRUNCATE_CHOP << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA30_AUDIOCIF_MONO_CONV_ZERO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA30_AUDIOCIF_MONO_CONV_COPY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_MASK (1 << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_ZERO (TEGRA30_AUDIOCIF_MONO_CONV_ZERO << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_COPY (TEGRA30_AUDIOCIF_MONO_CONV_COPY << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Registers within TEGRA30_AUDIO_CLUSTER_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* TEGRA30_AHUB_CHANNEL_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA30_AHUB_CHANNEL_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA30_AHUB_CHANNEL_CTRL_STRIDE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA30_AHUB_CHANNEL_CTRL_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA30_AHUB_CHANNEL_CTRL_TX_EN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA30_AHUB_CHANNEL_CTRL_RX_EN (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA30_AHUB_CHANNEL_CTRL_LOOPBACK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA30_PACK_8_4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA30_PACK_16 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* TEGRA30_AHUB_CHANNEL_CLEAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TEGRA30_AHUB_CHANNEL_CLEAR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TEGRA30_AHUB_CHANNEL_CLEAR_STRIDE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TEGRA30_AHUB_CHANNEL_CLEAR_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TEGRA30_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TEGRA30_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* TEGRA30_AHUB_CHANNEL_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TEGRA30_AHUB_CHANNEL_STATUS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TEGRA30_AHUB_CHANNEL_STATUS_STRIDE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TEGRA30_AHUB_CHANNEL_STATUS_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TEGRA30_AHUB_CHANNEL_STATUS_TX_TRIG (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TEGRA30_AHUB_CHANNEL_STATUS_RX_TRIG (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* TEGRA30_AHUB_CHANNEL_TXFIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TEGRA30_AHUB_CHANNEL_TXFIFO 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TEGRA30_AHUB_CHANNEL_TXFIFO_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* TEGRA30_AHUB_CHANNEL_RXFIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TEGRA30_AHUB_CHANNEL_RXFIFO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TEGRA30_AHUB_CHANNEL_RXFIFO_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* TEGRA30_AHUB_CIF_TX_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEGRA30_AHUB_CIF_TX_CTRL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TEGRA30_AHUB_CIF_TX_CTRL_STRIDE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TEGRA30_AHUB_CIF_TX_CTRL_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* TEGRA30_AHUB_CIF_RX_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TEGRA30_AHUB_CIF_RX_CTRL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TEGRA30_AHUB_CIF_RX_CTRL_STRIDE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TEGRA30_AHUB_CIF_RX_CTRL_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* TEGRA30_AHUB_CONFIG_LINK_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TEGRA30_AHUB_CONFIG_LINK_CTRL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CG_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TEGRA30_AHUB_CONFIG_LINK_CTRL_SOFT_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* TEGRA30_AHUB_MISC_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TEGRA30_AHUB_MISC_CTRL 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TEGRA30_AHUB_MISC_CTRL_AUDIO_ACTIVE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TEGRA30_AHUB_MISC_CTRL_AUDIO_CG_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK (0x1f << TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* TEGRA30_AHUB_APBDMA_LIVE_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* TEGRA30_AHUB_I2S_LIVE_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TEGRA30_AHUB_I2S_LIVE_STATUS 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* TEGRA30_AHUB_DAM0_LIVE_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define TEGRA30_AHUB_DAM_LIVE_STATUS 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define TEGRA30_AHUB_DAM_LIVE_STATUS_STRIDE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define TEGRA30_AHUB_DAM_LIVE_STATUS_COUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define TEGRA30_AHUB_DAM_LIVE_STATUS_TX_ENABLED (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1_ENABLED (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0_ENABLED (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* TEGRA30_AHUB_SPDIF_LIVE_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* TEGRA30_AHUB_I2S_INT_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TEGRA30_AHUB_I2S_INT_MASK 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* TEGRA30_AHUB_DAM_INT_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define TEGRA30_AHUB_DAM_INT_MASK 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* TEGRA30_AHUB_SPDIF_INT_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define TEGRA30_AHUB_SPDIF_INT_MASK 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* TEGRA30_AHUB_APBIF_INT_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TEGRA30_AHUB_APBIF_INT_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* TEGRA30_AHUB_I2S_INT_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define TEGRA30_AHUB_I2S_INT_STATUS 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* TEGRA30_AHUB_DAM_INT_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define TEGRA30_AHUB_DAM_INT_STATUS 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* TEGRA30_AHUB_SPDIF_INT_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define TEGRA30_AHUB_SPDIF_INT_STATUS 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* TEGRA30_AHUB_APBIF_INT_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define TEGRA30_AHUB_APBIF_INT_STATUS 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* TEGRA30_AHUB_I2S_INT_SOURCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define TEGRA30_AHUB_I2S_INT_SOURCE 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* TEGRA30_AHUB_DAM_INT_SOURCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define TEGRA30_AHUB_DAM_INT_SOURCE 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* TEGRA30_AHUB_SPDIF_INT_SOURCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define TEGRA30_AHUB_SPDIF_INT_SOURCE 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* TEGRA30_AHUB_APBIF_INT_SOURCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define TEGRA30_AHUB_APBIF_INT_SOURCE 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* TEGRA30_AHUB_I2S_INT_SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define TEGRA30_AHUB_I2S_INT_SET 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* TEGRA30_AHUB_DAM_INT_SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define TEGRA30_AHUB_DAM_INT_SET 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* TEGRA30_AHUB_SPDIF_INT_SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define TEGRA30_AHUB_SPDIF_INT_SET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* TEGRA30_AHUB_APBIF_INT_SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define TEGRA30_AHUB_APBIF_INT_SET 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Registers within TEGRA30_AHUB_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define TEGRA30_AHUB_AUDIO_RX 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define TEGRA30_AHUB_AUDIO_RX_STRIDE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TEGRA30_AHUB_AUDIO_RX_COUNT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* This register repeats once for each entry in enum tegra30_ahub_rxcif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* The fields in this register are 1 bit per entry in tegra30_ahub_txcif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * Terminology:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * I2S controllers, SPDIF controllers, and DAMs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * XBAR: The core cross-bar component of the AHUB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * CIF: Client Interface; the HW module connecting an audio device to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * XBAR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * DAM: Digital Audio Mixer: A HW module that mixes multiple audio streams,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * possibly including sample-rate conversion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * transmitted by a particular TX CIF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * This driver is currently very simplistic; many HW features are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * exposed; DAMs are not supported, only 16-bit stereo audio is supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) enum tegra30_ahub_txcif {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) TEGRA30_AHUB_TXCIF_APBIF_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) TEGRA30_AHUB_TXCIF_APBIF_TX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) TEGRA30_AHUB_TXCIF_APBIF_TX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) TEGRA30_AHUB_TXCIF_APBIF_TX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) TEGRA30_AHUB_TXCIF_I2S0_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) TEGRA30_AHUB_TXCIF_I2S1_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) TEGRA30_AHUB_TXCIF_I2S2_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) TEGRA30_AHUB_TXCIF_I2S3_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) TEGRA30_AHUB_TXCIF_I2S4_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) TEGRA30_AHUB_TXCIF_DAM0_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) TEGRA30_AHUB_TXCIF_DAM1_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) TEGRA30_AHUB_TXCIF_DAM2_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) TEGRA30_AHUB_TXCIF_SPDIF_TX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) TEGRA30_AHUB_TXCIF_SPDIF_TX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) enum tegra30_ahub_rxcif {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) TEGRA30_AHUB_RXCIF_APBIF_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) TEGRA30_AHUB_RXCIF_APBIF_RX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) TEGRA30_AHUB_RXcIF_APBIF_RX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) TEGRA30_AHUB_RXCIF_APBIF_RX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) TEGRA30_AHUB_RXCIF_I2S0_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) TEGRA30_AHUB_RXCIF_I2S1_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) TEGRA30_AHUB_RXCIF_I2S2_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) TEGRA30_AHUB_RXCIF_I2S3_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) TEGRA30_AHUB_RXCIF_I2S4_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) TEGRA30_AHUB_RXCIF_DAM0_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) TEGRA30_AHUB_RXCIF_DAM0_RX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) TEGRA30_AHUB_RXCIF_DAM1_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) TEGRA30_AHUB_RXCIF_DAM2_RX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) TEGRA30_AHUB_RXCIF_DAM3_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) TEGRA30_AHUB_RXCIF_DAM3_RX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) TEGRA30_AHUB_RXCIF_SPDIF_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) TEGRA30_AHUB_RXCIF_SPDIF_RX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) char *dmachan, int dmachan_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dma_addr_t *fiforeg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) char *dmachan, int dmachan_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dma_addr_t *fiforeg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) extern int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) enum tegra30_ahub_txcif txcif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct tegra30_ahub_cif_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned int threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) unsigned int audio_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned int client_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned int audio_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned int client_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned int expand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned int stereo_conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned int replicate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned int direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int truncate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned int mono_conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct tegra30_ahub_cif_conf *conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct tegra30_ahub_cif_conf *conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct tegra30_ahub_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 mod_list_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) void (*set_audio_cif)(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct tegra30_ahub_cif_conf *conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * FIXME: There are many more differences in HW, such as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * - More APBIF channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * - Extra separate chunks of register address space to represent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * the extra APBIF channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * - More units connected to the AHUB, so that tegra30_ahub_[rt]xcif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * need expansion, coupled with there being more defined bits in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * the AHUB routing registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * However, the driver doesn't support those new features yet, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * don't represent them here yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct tegra30_ahub {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) const struct tegra30_ahub_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct clk *clk_d_audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct clk *clk_apbif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) resource_size_t apbif_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct regmap *regmap_apbif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct regmap *regmap_ahub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) DECLARE_BITMAP(rx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) DECLARE_BITMAP(tx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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