^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tegra210_i2s.h - Definitions for Tegra210 I2S driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __TEGRA210_I2S_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __TEGRA210_I2S_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Register offsets from I2S*_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TEGRA210_I2S_RX_ENABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA210_I2S_RX_SOFT_RESET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA210_I2S_RX_STATUS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA210_I2S_RX_INT_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA210_I2S_RX_INT_MASK 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA210_I2S_RX_INT_SET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA210_I2S_RX_INT_CLEAR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA210_I2S_RX_CIF_CTRL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA210_I2S_RX_CTRL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA210_I2S_RX_SLOT_CTRL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA210_I2S_RX_CLK_TRIM 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA210_I2S_RX_CYA 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA210_I2S_RX_CIF_FIFO_STATUS 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA210_I2S_TX_ENABLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA210_I2S_TX_SOFT_RESET 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA210_I2S_TX_STATUS 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA210_I2S_TX_INT_STATUS 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA210_I2S_TX_INT_MASK 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA210_I2S_TX_INT_SET 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA210_I2S_TX_INT_CLEAR 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA210_I2S_TX_CIF_CTRL 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA210_I2S_TX_CTRL 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA210_I2S_TX_SLOT_CTRL 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA210_I2S_TX_CLK_TRIM 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA210_I2S_TX_CYA 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA210_I2S_TX_CIF_FIFO_STATUS 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA210_I2S_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA210_I2S_SOFT_RESET 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA210_I2S_CG 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA210_I2S_STATUS 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA210_I2S_INT_STATUS 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA210_I2S_CTRL 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA210_I2S_TIMING 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA210_I2S_SLOT_CTRL 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA210_I2S_CLK_TRIM 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA210_I2S_CYA 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Bit fields, shifts and masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2S_DATA_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I2S_CTRL_DATA_OFFSET_MASK (0x7ff << I2S_DATA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2S_EN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2S_EN_MASK BIT(I2S_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2S_EN BIT(I2S_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2S_FSYNC_WIDTH_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I2S_CTRL_FSYNC_WIDTH_MASK (0xff << I2S_FSYNC_WIDTH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2S_POS_EDGE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2S_NEG_EDGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2S_EDGE_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2S_CTRL_EDGE_CTRL_MASK BIT(I2S_EDGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define I2S_CTRL_EDGE_CTRL_POS_EDGE (I2S_POS_EDGE << I2S_EDGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define I2S_CTRL_EDGE_CTRL_NEG_EDGE (I2S_NEG_EDGE << I2S_EDGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define I2S_FMT_LRCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I2S_FMT_FSYNC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define I2S_FMT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define I2S_CTRL_FRAME_FMT_MASK (7 << I2S_FMT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define I2S_CTRL_FRAME_FMT_LRCK_MODE (I2S_FMT_LRCK << I2S_FMT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I2S_CTRL_FRAME_FMT_FSYNC_MODE (I2S_FMT_FSYNC << I2S_FMT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define I2S_CTRL_MASTER_EN_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I2S_CTRL_MASTER_EN_MASK BIT(I2S_CTRL_MASTER_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define I2S_CTRL_MASTER_EN BIT(I2S_CTRL_MASTER_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define I2S_CTRL_LRCK_POL_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define I2S_CTRL_LRCK_POL_MASK BIT(I2S_CTRL_LRCK_POL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define I2S_CTRL_LRCK_POL_LOW (0 << I2S_CTRL_LRCK_POL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define I2S_CTRL_LRCK_POL_HIGH BIT(I2S_CTRL_LRCK_POL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define I2S_CTRL_LPBK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define I2S_CTRL_LPBK_MASK BIT(I2S_CTRL_LPBK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define I2S_CTRL_LPBK_EN BIT(I2S_CTRL_LPBK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define I2S_BITS_8 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define I2S_BITS_16 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define I2S_BITS_32 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define I2S_CTRL_BIT_SIZE_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define I2S_TIMING_CH_BIT_CNT_MASK 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define I2S_TIMING_CH_BIT_CNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define I2S_SOFT_RESET_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define I2S_SOFT_RESET_MASK BIT(I2S_SOFT_RESET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define I2S_SOFT_RESET_EN BIT(I2S_SOFT_RESET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define I2S_RX_FIFO_DEPTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DEFAULT_I2S_RX_FIFO_THRESHOLD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DEFAULT_I2S_SLOT_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) enum tegra210_i2s_path {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) I2S_RX_PATH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) I2S_TX_PATH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) I2S_PATHS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct tegra210_i2s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct clk *clk_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct clk *clk_sync_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int stereo_to_mono[I2S_PATHS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int mono_to_stereo[I2S_PATHS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int dai_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int fsync_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int bclk_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int rx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int rx_fifo_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bool loopback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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