^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // tegra210_i2s.c - Tegra210 I2S driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "tegra210_i2s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "tegra_cif.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct reg_default tegra210_i2s_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { TEGRA210_I2S_RX_INT_MASK, 0x00000003 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { TEGRA210_I2S_RX_CIF_CTRL, 0x00007700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { TEGRA210_I2S_TX_INT_MASK, 0x00000003 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { TEGRA210_I2S_TX_CIF_CTRL, 0x00007700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { TEGRA210_I2S_CG, 0x1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { TEGRA210_I2S_TIMING, 0x0000001f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { TEGRA210_I2S_ENABLE, 0x1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Below update does not have any effect on Tegra186 and Tegra194.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * On Tegra210, I2S4 has "i2s4a" and "i2s4b" pins and below update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * is required to select i2s4b for it to be functional for I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { TEGRA210_I2S_CYA, 0x1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void tegra210_i2s_set_slot_ctrl(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int total_slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int tx_slot_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int rx_slot_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) regmap_write(regmap, TEGRA210_I2S_SLOT_CTRL, total_slots - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) regmap_write(regmap, TEGRA210_I2S_TX_SLOT_CTRL, tx_slot_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) regmap_write(regmap, TEGRA210_I2S_RX_SLOT_CTRL, rx_slot_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int tegra210_i2s_set_clock_rate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int clock_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct tegra210_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* No need to set rates if I2S is being operated in slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (!(val & I2S_CTRL_MASTER_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) err = clk_set_rate(i2s->clk_i2s, clock_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clock_rate, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!IS_ERR(i2s->clk_sync_input)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Other I/O modules in AHUB can use i2s bclk as reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * clock. Below sets sync input clock rate as per bclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * which can be used as input to other I/O modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) err = clk_set_rate(i2s->clk_sync_input, clock_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "can't set I2S sync input rate %u, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) clock_rate, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int tegra210_i2s_sw_reset(struct snd_soc_component *compnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) bool is_playback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct device *dev = compnt->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct tegra210_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int reset_mask = I2S_SOFT_RESET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int reset_en = I2S_SOFT_RESET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int reset_reg, cif_reg, stream_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int cif_ctrl, stream_ctrl, i2s_ctrl, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (is_playback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reset_reg = TEGRA210_I2S_RX_SOFT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cif_reg = TEGRA210_I2S_RX_CIF_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) stream_reg = TEGRA210_I2S_RX_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reset_reg = TEGRA210_I2S_TX_SOFT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) cif_reg = TEGRA210_I2S_TX_CIF_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) stream_reg = TEGRA210_I2S_TX_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Store CIF and I2S control values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) regmap_read(i2s->regmap, cif_reg, &cif_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) regmap_read(i2s->regmap, stream_reg, &stream_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &i2s_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Reset to make sure the previous transactions are clean */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) err = regmap_read_poll_timeout(i2s->regmap, reset_reg, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) !(val & reset_mask & reset_en),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 10, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_err(dev, "timeout: failed to reset I2S for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) is_playback ? "playback" : "capture");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Restore CIF and I2S control values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) regmap_write(i2s->regmap, cif_reg, cif_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) regmap_write(i2s->regmap, stream_reg, stream_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) regmap_write(i2s->regmap, TEGRA210_I2S_CTRL, i2s_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int tegra210_i2s_init(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct snd_kcontrol *kcontrol, int event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct snd_soc_component *compnt = snd_soc_dapm_to_component(w->dapm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct device *dev = compnt->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct tegra210_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int val, status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool is_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) switch (w->reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case TEGRA210_I2S_RX_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) is_playback = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) status_reg = TEGRA210_I2S_RX_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case TEGRA210_I2S_TX_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) is_playback = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) status_reg = TEGRA210_I2S_TX_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Ensure I2S is in disabled state before new session */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) err = regmap_read_poll_timeout(i2s->regmap, status_reg, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) !(val & I2S_EN_MASK & I2S_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 10, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_err(dev, "timeout: previous I2S %s is still active\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) is_playback ? "playback" : "capture");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return tegra210_i2s_sw_reset(compnt, is_playback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int __maybe_unused tegra210_i2s_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct tegra210_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) regcache_cache_only(i2s->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) regcache_mark_dirty(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) clk_disable_unprepare(i2s->clk_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int __maybe_unused tegra210_i2s_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct tegra210_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) err = clk_prepare_enable(i2s->clk_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev_err(dev, "failed to enable I2S bit clock, err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) regcache_cache_only(i2s->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) regcache_sync(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int data_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Capture path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) regmap_update_bits(i2s->regmap, TEGRA210_I2S_TX_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) I2S_CTRL_DATA_OFFSET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) data_offset << I2S_DATA_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Playback path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) regmap_update_bits(i2s->regmap, TEGRA210_I2S_RX_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) I2S_CTRL_DATA_OFFSET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) data_offset << I2S_DATA_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int tegra210_i2s_set_fmt(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mask = I2S_CTRL_MASTER_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) val = I2S_CTRL_MASTER_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mask |= I2S_CTRL_FRAME_FMT_MASK | I2S_CTRL_LRCK_POL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val |= I2S_CTRL_LRCK_POL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) tegra210_i2s_set_data_offset(i2s, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val |= I2S_CTRL_LRCK_POL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) tegra210_i2s_set_data_offset(i2s, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* I2S mode has data offset of 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) val |= I2S_CTRL_LRCK_POL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) tegra210_i2s_set_data_offset(i2s, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * For RJ mode data offset is dependent on the sample size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * and the bclk ratio, and so is set when hw_params is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) val |= I2S_CTRL_LRCK_POL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) val |= I2S_CTRL_FRAME_FMT_LRCK_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) val |= I2S_CTRL_LRCK_POL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) tegra210_i2s_set_data_offset(i2s, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mask |= I2S_CTRL_EDGE_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) val |= I2S_CTRL_EDGE_CTRL_POS_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val |= I2S_CTRL_EDGE_CTRL_POS_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) val ^= I2S_CTRL_LRCK_POL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) val |= I2S_CTRL_EDGE_CTRL_NEG_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) val |= I2S_CTRL_EDGE_CTRL_NEG_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) val ^= I2S_CTRL_LRCK_POL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) i2s->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int tegra210_i2s_set_tdm_slot(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int tx_mask, unsigned int rx_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int slots, int slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Copy the required tx and rx mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) i2s->tx_mask = (tx_mask > DEFAULT_I2S_SLOT_MASK) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DEFAULT_I2S_SLOT_MASK : tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) i2s->rx_mask = (rx_mask > DEFAULT_I2S_SLOT_MASK) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) DEFAULT_I2S_SLOT_MASK : rx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int tegra210_i2s_get_loopback(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ucontrol->value.integer.value[0] = i2s->loopback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int tegra210_i2s_put_loopback(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int value = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (value == i2s->loopback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) i2s->loopback = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, I2S_CTRL_LPBK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) i2s->loopback << I2S_CTRL_LPBK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int tegra210_i2s_get_fsync_width(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ucontrol->value.integer.value[0] = i2s->fsync_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int tegra210_i2s_put_fsync_width(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int value = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (value == i2s->fsync_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) i2s->fsync_width = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Frame sync width is used only for FSYNC modes and not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * applicable for LRCK modes. Reset value for this field is "0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * which means the width is one bit clock wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * The width requirement may depend on the codec and in such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * cases mixer control is used to update custom values. A value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * of "N" here means, width is "N + 1" bit clock wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) I2S_CTRL_FSYNC_WIDTH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) i2s->fsync_width << I2S_FSYNC_WIDTH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int tegra210_i2s_cget_stereo_to_mono(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_TX_PATH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int tegra210_i2s_cput_stereo_to_mono(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (value == i2s->stereo_to_mono[I2S_TX_PATH])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) i2s->stereo_to_mono[I2S_TX_PATH] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int tegra210_i2s_cget_mono_to_stereo(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_TX_PATH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int tegra210_i2s_cput_mono_to_stereo(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (value == i2s->mono_to_stereo[I2S_TX_PATH])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) i2s->mono_to_stereo[I2S_TX_PATH] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int tegra210_i2s_pget_stereo_to_mono(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ucontrol->value.enumerated.item[0] = i2s->stereo_to_mono[I2S_RX_PATH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int tegra210_i2s_pput_stereo_to_mono(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (value == i2s->stereo_to_mono[I2S_RX_PATH])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) i2s->stereo_to_mono[I2S_RX_PATH] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int tegra210_i2s_pget_mono_to_stereo(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ucontrol->value.enumerated.item[0] = i2s->mono_to_stereo[I2S_RX_PATH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int tegra210_i2s_pput_mono_to_stereo(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (value == i2s->mono_to_stereo[I2S_RX_PATH])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) i2s->mono_to_stereo[I2S_RX_PATH] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int tegra210_i2s_pget_fifo_th(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ucontrol->value.integer.value[0] = i2s->rx_fifo_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int tegra210_i2s_pput_fifo_th(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int value = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (value == i2s->rx_fifo_th)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) i2s->rx_fifo_th = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int tegra210_i2s_get_bclk_ratio(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ucontrol->value.integer.value[0] = i2s->bclk_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int tegra210_i2s_put_bclk_ratio(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct snd_soc_component *compnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int value = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (value == i2s->bclk_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) i2s->bclk_ratio = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int tegra210_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned int ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) i2s->bclk_ratio = ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int tegra210_i2s_set_timing_params(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned int sample_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned int srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct tegra210_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned int val, bit_count, bclk_rate, num_bclk = sample_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (i2s->bclk_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) num_bclk *= i2s->bclk_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (i2s->dai_fmt == SND_SOC_DAIFMT_RIGHT_J)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) tegra210_i2s_set_data_offset(i2s, num_bclk - sample_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* I2S bit clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) bclk_rate = srate * channels * num_bclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) err = tegra210_i2s_set_clock_rate(dev, bclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) bclk_rate, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * For LRCK mode, channel bit count depends on number of bit clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * on the left channel, where as for FSYNC mode bit count depends on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * the number of bit clocks in both left and right channels for DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * mode or the number of bit clocks in one TDM frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) switch (val & I2S_CTRL_FRAME_FMT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case I2S_CTRL_FRAME_FMT_LRCK_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) bit_count = (bclk_rate / (srate * 2)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case I2S_CTRL_FRAME_FMT_FSYNC_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) bit_count = (bclk_rate / srate) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) tegra210_i2s_set_slot_ctrl(i2s->regmap, channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) i2s->tx_mask, i2s->rx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_err(dev, "invalid I2S frame format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (bit_count > I2S_TIMING_CH_BIT_CNT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_err(dev, "invalid I2S channel bit count %u\n", bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) regmap_write(i2s->regmap, TEGRA210_I2S_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) bit_count << I2S_TIMING_CH_BIT_CNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int tegra210_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct device *dev = dai->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned int sample_size, channels, srate, val, reg, path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct tegra_cif_conf cif_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (channels < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_err(dev, "invalid I2S %d channel configuration\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) cif_conf.audio_ch = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) cif_conf.client_ch = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case SNDRV_PCM_FORMAT_S8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) val = I2S_BITS_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) sample_size = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) cif_conf.audio_bits = TEGRA_ACIF_BITS_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) cif_conf.client_bits = TEGRA_ACIF_BITS_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) val = I2S_BITS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) sample_size = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) cif_conf.client_bits = TEGRA_ACIF_BITS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) val = I2S_BITS_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) sample_size = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) cif_conf.client_bits = TEGRA_ACIF_BITS_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dev_err(dev, "unsupported format!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Program sample size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) I2S_CTRL_BIT_SIZE_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) srate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* For playback I2S RX-CIF and for capture TX-CIF is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) path = I2S_RX_PATH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) path = I2S_TX_PATH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) unsigned int max_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* FIFO threshold in terms of frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) max_th = (I2S_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (i2s->rx_fifo_th > max_th)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) i2s->rx_fifo_th = max_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) cif_conf.threshold = i2s->rx_fifo_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) reg = TEGRA210_I2S_RX_CIF_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) reg = TEGRA210_I2S_TX_CIF_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) cif_conf.mono_conv = i2s->mono_to_stereo[path];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) cif_conf.stereo_conv = i2s->stereo_to_mono[path];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) tegra_set_cif(i2s->regmap, reg, &cif_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return tegra210_i2s_set_timing_params(dev, sample_size, srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) cif_conf.client_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static const struct snd_soc_dai_ops tegra210_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .set_fmt = tegra210_i2s_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .hw_params = tegra210_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .set_bclk_ratio = tegra210_i2s_set_dai_bclk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .set_tdm_slot = tegra210_i2s_set_tdm_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static struct snd_soc_dai_driver tegra210_i2s_dais[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .name = "I2S-CIF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .stream_name = "CIF-Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .channels_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .formats = SNDRV_PCM_FMTBIT_S8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .stream_name = "CIF-Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .channels_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .formats = SNDRV_PCM_FMTBIT_S8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .name = "I2S-DAP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .stream_name = "DAP-Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .channels_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .formats = SNDRV_PCM_FMTBIT_S8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .stream_name = "DAP-Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .channels_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .formats = SNDRV_PCM_FMTBIT_S8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .ops = &tegra210_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const char * const tegra210_i2s_stereo_conv_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) "CH0", "CH1", "AVG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const char * const tegra210_i2s_mono_conv_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) "Zero", "Copy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static const struct soc_enum tegra210_i2s_mono_conv_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_i2s_mono_conv_text),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) tegra210_i2s_mono_conv_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const struct soc_enum tegra210_i2s_stereo_conv_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_i2s_stereo_conv_text),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) tegra210_i2s_stereo_conv_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static const struct snd_kcontrol_new tegra210_i2s_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) SOC_SINGLE_EXT("Loopback", 0, 0, 1, 0, tegra210_i2s_get_loopback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) tegra210_i2s_put_loopback),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) SOC_SINGLE_EXT("FSYNC Width", 0, 0, 255, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) tegra210_i2s_get_fsync_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) tegra210_i2s_put_fsync_width),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) SOC_ENUM_EXT("Capture Stereo To Mono", tegra210_i2s_stereo_conv_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) tegra210_i2s_cget_stereo_to_mono,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) tegra210_i2s_cput_stereo_to_mono),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) SOC_ENUM_EXT("Capture Mono To Stereo", tegra210_i2s_mono_conv_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) tegra210_i2s_cget_mono_to_stereo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) tegra210_i2s_cput_mono_to_stereo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) SOC_ENUM_EXT("Playback Stereo To Mono", tegra210_i2s_stereo_conv_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) tegra210_i2s_pget_mono_to_stereo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) tegra210_i2s_pput_mono_to_stereo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) SOC_ENUM_EXT("Playback Mono To Stereo", tegra210_i2s_mono_conv_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) tegra210_i2s_pget_stereo_to_mono,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) tegra210_i2s_pput_stereo_to_mono),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) SOC_SINGLE_EXT("Playback FIFO Threshold", 0, 0, I2S_RX_FIFO_DEPTH - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 0, tegra210_i2s_pget_fifo_th, tegra210_i2s_pput_fifo_th),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) SOC_SINGLE_EXT("BCLK Ratio", 0, 0, INT_MAX, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) tegra210_i2s_get_bclk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) tegra210_i2s_put_bclk_ratio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const struct snd_soc_dapm_widget tegra210_i2s_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) SND_SOC_DAPM_AIF_IN_E("RX", NULL, 0, TEGRA210_I2S_RX_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) SND_SOC_DAPM_AIF_OUT_E("TX", NULL, 0, TEGRA210_I2S_TX_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 0, 0, tegra210_i2s_init, SND_SOC_DAPM_PRE_PMU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) SND_SOC_DAPM_MIC("MIC", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) SND_SOC_DAPM_SPK("SPK", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const struct snd_soc_dapm_route tegra210_i2s_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* Playback route from XBAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) { "XBAR-Playback", NULL, "XBAR-TX" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) { "CIF-Playback", NULL, "XBAR-Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) { "RX", NULL, "CIF-Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) { "DAP-Playback", NULL, "RX" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) { "SPK", NULL, "DAP-Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* Capture route to XBAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) { "XBAR-RX", NULL, "XBAR-Capture" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) { "XBAR-Capture", NULL, "CIF-Capture" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) { "CIF-Capture", NULL, "TX" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) { "TX", NULL, "DAP-Capture" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) { "DAP-Capture", NULL, "MIC" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static const struct snd_soc_component_driver tegra210_i2s_cmpnt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .dapm_widgets = tegra210_i2s_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .num_dapm_widgets = ARRAY_SIZE(tegra210_i2s_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .dapm_routes = tegra210_i2s_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .num_dapm_routes = ARRAY_SIZE(tegra210_i2s_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .controls = tegra210_i2s_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .num_controls = ARRAY_SIZE(tegra210_i2s_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .non_legacy_dai_naming = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static bool tegra210_i2s_wr_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) case TEGRA210_I2S_RX_ENABLE ... TEGRA210_I2S_RX_SOFT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) case TEGRA210_I2S_RX_INT_MASK ... TEGRA210_I2S_RX_CLK_TRIM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case TEGRA210_I2S_TX_ENABLE ... TEGRA210_I2S_TX_SOFT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) case TEGRA210_I2S_TX_INT_MASK ... TEGRA210_I2S_TX_CLK_TRIM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) case TEGRA210_I2S_ENABLE ... TEGRA210_I2S_CG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case TEGRA210_I2S_CTRL ... TEGRA210_I2S_CYA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static bool tegra210_i2s_rd_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (tegra210_i2s_wr_reg(dev, reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case TEGRA210_I2S_RX_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) case TEGRA210_I2S_RX_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case TEGRA210_I2S_RX_CIF_FIFO_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case TEGRA210_I2S_TX_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) case TEGRA210_I2S_TX_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case TEGRA210_I2S_TX_CIF_FIFO_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) case TEGRA210_I2S_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case TEGRA210_I2S_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static bool tegra210_i2s_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) case TEGRA210_I2S_RX_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) case TEGRA210_I2S_RX_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case TEGRA210_I2S_RX_CIF_FIFO_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case TEGRA210_I2S_TX_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) case TEGRA210_I2S_TX_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) case TEGRA210_I2S_TX_CIF_FIFO_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) case TEGRA210_I2S_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) case TEGRA210_I2S_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case TEGRA210_I2S_RX_SOFT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) case TEGRA210_I2S_TX_SOFT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const struct regmap_config tegra210_i2s_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .max_register = TEGRA210_I2S_CYA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .writeable_reg = tegra210_i2s_wr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .readable_reg = tegra210_i2s_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .volatile_reg = tegra210_i2s_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .reg_defaults = tegra210_i2s_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .num_reg_defaults = ARRAY_SIZE(tegra210_i2s_reg_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int tegra210_i2s_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct tegra210_i2s *i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (!i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) i2s->rx_fifo_th = DEFAULT_I2S_RX_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) i2s->tx_mask = DEFAULT_I2S_SLOT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) i2s->rx_mask = DEFAULT_I2S_SLOT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) i2s->loopback = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_set_drvdata(dev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) i2s->clk_i2s = devm_clk_get(dev, "i2s");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (IS_ERR(i2s->clk_i2s)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dev_err(dev, "can't retrieve I2S bit clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return PTR_ERR(i2s->clk_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * Not an error, as this clock is needed only when some other I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * requires input clock from current I2S instance, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * configurable from DT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) i2s->clk_sync_input = devm_clk_get(dev, "sync_input");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (IS_ERR(i2s->clk_sync_input))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev_dbg(dev, "can't retrieve I2S sync input clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) i2s->regmap = devm_regmap_init_mmio(dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) &tegra210_i2s_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (IS_ERR(i2s->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dev_err(dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return PTR_ERR(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) regcache_cache_only(i2s->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) err = devm_snd_soc_register_component(dev, &tegra210_i2s_cmpnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) tegra210_i2s_dais,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ARRAY_SIZE(tegra210_i2s_dais));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dev_err(dev, "can't register I2S component, err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int tegra210_i2s_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static const struct dev_pm_ops tegra210_i2s_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) SET_RUNTIME_PM_OPS(tegra210_i2s_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) tegra210_i2s_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static const struct of_device_id tegra210_i2s_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) { .compatible = "nvidia,tegra210-i2s" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) MODULE_DEVICE_TABLE(of, tegra210_i2s_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static struct platform_driver tegra210_i2s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .name = "tegra210-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .of_match_table = tegra210_i2s_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .pm = &tegra210_i2s_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .probe = tegra210_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .remove = tegra210_i2s_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) module_platform_driver(tegra210_i2s_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) MODULE_AUTHOR("Songhee Baek <sbaek@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) MODULE_DESCRIPTION("Tegra210 ASoC I2S driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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