^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tegra210_dmic.h - Definitions for Tegra210 DMIC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __TEGRA210_DMIC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __TEGRA210_DMIC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Register offsets from DMIC BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TEGRA210_DMIC_TX_STATUS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA210_DMIC_TX_INT_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA210_DMIC_TX_INT_MASK 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA210_DMIC_TX_INT_SET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA210_DMIC_TX_INT_CLEAR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA210_DMIC_TX_CIF_CTRL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA210_DMIC_ENABLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA210_DMIC_SOFT_RESET 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA210_DMIC_CG 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA210_DMIC_STATUS 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA210_DMIC_INT_STATUS 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA210_DMIC_CTRL 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA210_DMIC_DBG_CTRL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA210_DMIC_LP_FILTER_GAIN 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_0 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_1 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_2 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_3 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_4 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_0 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_1 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_2 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_3 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_4 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Fields in TEGRA210_DMIC_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CH_SEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA210_DMIC_CTRL_CHANNEL_SELECT_MASK (0x3 << CH_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LRSEL_POL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA210_DMIC_CTRL_LRSEL_POLARITY_MASK (0x1 << LRSEL_POL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OSR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA210_DMIC_CTRL_OSR_MASK (0x3 << OSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DMIC_OSR_FACTOR 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DEFAULT_GAIN_Q23 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Max boost gain factor used for mixer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MAX_BOOST_GAIN 25599
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enum tegra_dmic_ch_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DMIC_CH_SELECT_LEFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DMIC_CH_SELECT_RIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DMIC_CH_SELECT_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum tegra_dmic_osr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DMIC_OSR_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DMIC_OSR_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DMIC_OSR_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) enum tegra_dmic_lrsel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DMIC_LRSEL_LEFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DMIC_LRSEL_RIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct tegra210_dmic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk *clk_dmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int mono_to_stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int stereo_to_mono;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int boost_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int ch_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int osr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int lrsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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