^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // tegra210_dmic.c - Tegra210 DMIC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "tegra210_dmic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "tegra_cif.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct reg_default tegra210_dmic_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { TEGRA210_DMIC_TX_INT_MASK, 0x00000001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { TEGRA210_DMIC_TX_CIF_CTRL, 0x00007700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { TEGRA210_DMIC_CG, 0x1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { TEGRA210_DMIC_CTRL, 0x00000301 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Below enables all filters - DCR, LP and SC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { TEGRA210_DMIC_DBG_CTRL, 0xe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Below as per latest POR value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* LP filter is configured for pass through and used to apply gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { TEGRA210_DMIC_LP_BIQUAD_0_COEF_0, 0x00800000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { TEGRA210_DMIC_LP_BIQUAD_0_COEF_1, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { TEGRA210_DMIC_LP_BIQUAD_0_COEF_2, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { TEGRA210_DMIC_LP_BIQUAD_0_COEF_3, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { TEGRA210_DMIC_LP_BIQUAD_0_COEF_4, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { TEGRA210_DMIC_LP_BIQUAD_1_COEF_0, 0x00800000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { TEGRA210_DMIC_LP_BIQUAD_1_COEF_1, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { TEGRA210_DMIC_LP_BIQUAD_1_COEF_2, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { TEGRA210_DMIC_LP_BIQUAD_1_COEF_3, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { TEGRA210_DMIC_LP_BIQUAD_1_COEF_4, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int __maybe_unused tegra210_dmic_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct tegra210_dmic *dmic = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) regcache_cache_only(dmic->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) regcache_mark_dirty(dmic->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) clk_disable_unprepare(dmic->clk_dmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int __maybe_unused tegra210_dmic_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct tegra210_dmic *dmic = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) err = clk_prepare_enable(dmic->clk_dmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dev_err(dev, "failed to enable DMIC clock, err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) regcache_cache_only(dmic->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) regcache_sync(dmic->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int tegra210_dmic_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct tegra210_dmic *dmic = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int srate, clk_rate, channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct tegra_cif_conf cif_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long long gain_q23 = DEFAULT_GAIN_Q23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) cif_conf.audio_ch = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) switch (dmic->ch_select) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case DMIC_CH_SELECT_LEFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case DMIC_CH_SELECT_RIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) cif_conf.client_ch = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case DMIC_CH_SELECT_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) cif_conf.client_ch = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dev_err(dai->dev, "invalid DMIC client channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) srate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * DMIC clock rate is a multiple of 'Over Sampling Ratio' and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * 'Sample Rate'. The supported OSR values are 64, 128 and 256.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clk_rate = (DMIC_OSR_FACTOR << dmic->osr_val) * srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) err = clk_set_rate(dmic->clk_dmic, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dev_err(dai->dev, "can't set DMIC clock rate %u, err: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clk_rate, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) regmap_update_bits(dmic->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) TEGRA210_DMIC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) TEGRA210_DMIC_CTRL_LRSEL_POLARITY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) TEGRA210_DMIC_CTRL_OSR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) TEGRA210_DMIC_CTRL_CHANNEL_SELECT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) (dmic->lrsel << LRSEL_POL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) (dmic->osr_val << OSR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ((dmic->ch_select + 1) << CH_SEL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Use LP filter gain register to apply boost.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Boost Gain Volume control has 100x factor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (dmic->boost_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) gain_q23 = div_u64(gain_q23 * dmic->boost_gain, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) regmap_write(dmic->regmap, TEGRA210_DMIC_LP_FILTER_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) (unsigned int)gain_q23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(dai->dev, "unsupported format!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cif_conf.client_bits = TEGRA_ACIF_BITS_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) cif_conf.mono_conv = dmic->mono_to_stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) cif_conf.stereo_conv = dmic->stereo_to_mono;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tegra_set_cif(dmic->regmap, TEGRA210_DMIC_TX_CIF_CTRL, &cif_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int tegra210_dmic_get_boost_gain(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ucontrol->value.integer.value[0] = dmic->boost_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int tegra210_dmic_put_boost_gain(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int value = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (value == dmic->boost_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dmic->boost_gain = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int tegra210_dmic_get_ch_select(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ucontrol->value.enumerated.item[0] = dmic->ch_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int tegra210_dmic_put_ch_select(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (value == dmic->ch_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dmic->ch_select = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int tegra210_dmic_get_mono_to_stereo(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ucontrol->value.enumerated.item[0] = dmic->mono_to_stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int tegra210_dmic_put_mono_to_stereo(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (value == dmic->mono_to_stereo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dmic->mono_to_stereo = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int tegra210_dmic_get_stereo_to_mono(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ucontrol->value.enumerated.item[0] = dmic->stereo_to_mono;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int tegra210_dmic_put_stereo_to_mono(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (value == dmic->stereo_to_mono)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dmic->stereo_to_mono = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int tegra210_dmic_get_osr_val(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ucontrol->value.enumerated.item[0] = dmic->osr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int tegra210_dmic_put_osr_val(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (value == dmic->osr_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dmic->osr_val = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int tegra210_dmic_get_pol_sel(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ucontrol->value.enumerated.item[0] = dmic->lrsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int tegra210_dmic_put_pol_sel(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (value == dmic->lrsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dmic->lrsel = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct snd_soc_dai_ops tegra210_dmic_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .hw_params = tegra210_dmic_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct snd_soc_dai_driver tegra210_dmic_dais[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .name = "DMIC-CIF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .stream_name = "CIF-Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .name = "DMIC-DAP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .stream_name = "DAP-Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .ops = &tegra210_dmic_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct snd_soc_dapm_widget tegra210_dmic_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SND_SOC_DAPM_AIF_OUT("TX", NULL, 0, TEGRA210_DMIC_ENABLE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) SND_SOC_DAPM_MIC("MIC", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const struct snd_soc_dapm_route tegra210_dmic_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { "XBAR-RX", NULL, "XBAR-Capture" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { "XBAR-Capture", NULL, "CIF-Capture" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { "CIF-Capture", NULL, "TX" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { "TX", NULL, "DAP-Capture" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { "DAP-Capture", NULL, "MIC" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const char * const tegra210_dmic_ch_select[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "Left", "Right", "Stereo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct soc_enum tegra210_dmic_ch_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_ch_select),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) tegra210_dmic_ch_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const char * const tegra210_dmic_mono_conv_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "Zero", "Copy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const char * const tegra210_dmic_stereo_conv_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "CH0", "CH1", "AVG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct soc_enum tegra210_dmic_mono_conv_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_mono_conv_text),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) tegra210_dmic_mono_conv_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct soc_enum tegra210_dmic_stereo_conv_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_stereo_conv_text),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) tegra210_dmic_stereo_conv_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const char * const tegra210_dmic_osr_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "OSR_64", "OSR_128", "OSR_256",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct soc_enum tegra210_dmic_osr_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_osr_text),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) tegra210_dmic_osr_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const char * const tegra210_dmic_lrsel_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "Left", "Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct soc_enum tegra210_dmic_lrsel_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_lrsel_text),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) tegra210_dmic_lrsel_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const struct snd_kcontrol_new tegra210_dmic_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) SOC_SINGLE_EXT("Boost Gain Volume", 0, 0, MAX_BOOST_GAIN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) tegra210_dmic_get_boost_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) tegra210_dmic_put_boost_gain),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) SOC_ENUM_EXT("Channel Select", tegra210_dmic_ch_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) tegra210_dmic_get_ch_select, tegra210_dmic_put_ch_select),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) SOC_ENUM_EXT("Mono To Stereo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) tegra210_dmic_mono_conv_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) tegra210_dmic_get_mono_to_stereo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) tegra210_dmic_put_mono_to_stereo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) SOC_ENUM_EXT("Stereo To Mono",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) tegra210_dmic_stereo_conv_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) tegra210_dmic_get_stereo_to_mono,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) tegra210_dmic_put_stereo_to_mono),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) SOC_ENUM_EXT("OSR Value", tegra210_dmic_osr_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) tegra210_dmic_get_osr_val, tegra210_dmic_put_osr_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) SOC_ENUM_EXT("LR Polarity Select", tegra210_dmic_lrsel_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) tegra210_dmic_get_pol_sel, tegra210_dmic_put_pol_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const struct snd_soc_component_driver tegra210_dmic_compnt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .dapm_widgets = tegra210_dmic_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .num_dapm_widgets = ARRAY_SIZE(tegra210_dmic_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .dapm_routes = tegra210_dmic_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .num_dapm_routes = ARRAY_SIZE(tegra210_dmic_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .controls = tegra210_dmic_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .num_controls = ARRAY_SIZE(tegra210_dmic_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static bool tegra210_dmic_wr_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case TEGRA210_DMIC_TX_INT_MASK ... TEGRA210_DMIC_TX_CIF_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case TEGRA210_DMIC_ENABLE ... TEGRA210_DMIC_CG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case TEGRA210_DMIC_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case TEGRA210_DMIC_DBG_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4 ... TEGRA210_DMIC_LP_BIQUAD_1_COEF_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static bool tegra210_dmic_rd_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (tegra210_dmic_wr_reg(dev, reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case TEGRA210_DMIC_TX_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case TEGRA210_DMIC_TX_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case TEGRA210_DMIC_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case TEGRA210_DMIC_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static bool tegra210_dmic_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case TEGRA210_DMIC_TX_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case TEGRA210_DMIC_TX_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case TEGRA210_DMIC_TX_INT_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case TEGRA210_DMIC_SOFT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case TEGRA210_DMIC_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case TEGRA210_DMIC_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct regmap_config tegra210_dmic_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .max_register = TEGRA210_DMIC_LP_BIQUAD_1_COEF_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .writeable_reg = tegra210_dmic_wr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .readable_reg = tegra210_dmic_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .volatile_reg = tegra210_dmic_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .reg_defaults = tegra210_dmic_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .num_reg_defaults = ARRAY_SIZE(tegra210_dmic_reg_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int tegra210_dmic_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct tegra210_dmic *dmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dmic = devm_kzalloc(dev, sizeof(*dmic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!dmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dmic->osr_val = DMIC_OSR_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dmic->ch_select = DMIC_CH_SELECT_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dmic->lrsel = DMIC_LRSEL_LEFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dmic->boost_gain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dmic->stereo_to_mono = 0; /* "CH0" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_set_drvdata(dev, dmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dmic->clk_dmic = devm_clk_get(dev, "dmic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (IS_ERR(dmic->clk_dmic)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(dev, "can't retrieve DMIC clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return PTR_ERR(dmic->clk_dmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dmic->regmap = devm_regmap_init_mmio(dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) &tegra210_dmic_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (IS_ERR(dmic->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_err(dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return PTR_ERR(dmic->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) regcache_cache_only(dmic->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) err = devm_snd_soc_register_component(dev, &tegra210_dmic_compnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) tegra210_dmic_dais,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ARRAY_SIZE(tegra210_dmic_dais));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_err(dev, "can't register DMIC component, err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int tegra210_dmic_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const struct dev_pm_ops tegra210_dmic_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) SET_RUNTIME_PM_OPS(tegra210_dmic_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) tegra210_dmic_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const struct of_device_id tegra210_dmic_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) { .compatible = "nvidia,tegra210-dmic" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MODULE_DEVICE_TABLE(of, tegra210_dmic_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static struct platform_driver tegra210_dmic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .name = "tegra210-dmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .of_match_table = tegra210_dmic_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .pm = &tegra210_dmic_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .probe = tegra210_dmic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .remove = tegra210_dmic_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) module_platform_driver(tegra210_dmic_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_AUTHOR("Rahul Mittal <rmittal@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MODULE_DESCRIPTION("Tegra210 ASoC DMIC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags