^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tegra210_ahub.h - TEGRA210 AHUB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __TEGRA210_AHUB__H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __TEGRA210_AHUB__H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Tegra210 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TEGRA210_XBAR_PART1_RX 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA210_XBAR_PART2_RX 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA210_XBAR_RX_STRIDE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA210_XBAR_AUDIO_RX_COUNT 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA210_XBAR_REG_MASK_0 0xf1f03ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA210_XBAR_REG_MASK_1 0x3f30031f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA210_XBAR_REG_MASK_2 0xff1cf313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA210_XBAR_REG_MASK_3 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA210_XBAR_UPDATE_MAX_REG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Tegra186 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA186_XBAR_PART3_RX 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA186_XBAR_AUDIO_RX_COUNT 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA186_XBAR_REG_MASK_0 0xf3fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA186_XBAR_REG_MASK_1 0x3f310f1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA186_XBAR_REG_MASK_2 0xff3cf311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA186_XBAR_REG_MASK_3 0x3f0f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA186_XBAR_UPDATE_MAX_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA186_XBAR_UPDATE_MAX_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) (TEGRA210_XBAR_RX_STRIDE * (TEGRA186_XBAR_AUDIO_RX_COUNT - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) (TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MUX_VALUE(npart, nbit) (1 + (nbit) + (npart) * 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SOC_VALUE_ENUM_WIDE(xreg, shift, xmax, xtexts, xvalues) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .reg = xreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .shift_l = shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .shift_r = shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .items = xmax, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .texts = xtexts, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .values = xvalues, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .mask = xmax ? roundup_pow_of_two(xmax) - 1 : 0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SOC_VALUE_ENUM_WIDE_DECL(name, xreg, shift, xtexts, xvalues) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct soc_enum name = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SOC_VALUE_ENUM_WIDE(xreg, shift, ARRAY_SIZE(xtexts), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) xtexts, xvalues)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MUX_ENUM_CTRL_DECL(ename, id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) tegra210_ahub_mux_texts, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) tegra210_ahub_mux_values); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const struct snd_kcontrol_new ename##_control = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SOC_DAPM_ENUM_EXT("Route", ename##_enum, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) tegra_ahub_get_value_enum, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) tegra_ahub_put_value_enum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MUX_ENUM_CTRL_DECL_186(ename, id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) tegra186_ahub_mux_texts, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) tegra186_ahub_mux_values); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct snd_kcontrol_new ename##_control = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SOC_DAPM_ENUM_EXT("Route", ename##_enum, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) tegra_ahub_get_value_enum, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) tegra_ahub_put_value_enum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define WIDGETS(sname, ename) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SND_SOC_DAPM_MUX(sname " Mux", SND_SOC_NOPM, 0, 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) &ename##_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TX_WIDGETS(sname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DAI(sname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .name = "XBAR-" #sname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .playback = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .stream_name = #sname " XBAR-Playback", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .channels_min = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .channels_max = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .rates = SNDRV_PCM_RATE_8000_192000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .formats = SNDRV_PCM_FMTBIT_S8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SNDRV_PCM_FMTBIT_S24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SNDRV_PCM_FMTBIT_S32_LE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .capture = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .stream_name = #sname " XBAR-Capture", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .channels_min = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .channels_max = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .rates = SNDRV_PCM_RATE_8000_192000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .formats = SNDRV_PCM_FMTBIT_S8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SNDRV_PCM_FMTBIT_S24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SNDRV_PCM_FMTBIT_S32_LE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct tegra_ahub_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const struct regmap_config *regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const struct snd_soc_component_driver *cmpnt_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct snd_soc_dai_driver *dai_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int mask[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int reg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int num_dais;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct tegra_ahub {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const struct tegra_ahub_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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