^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // tegra210_ahub.c - Tegra210 AHUB driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "tegra210_ahub.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static int tegra_ahub_get_value_enum(struct snd_kcontrol *kctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct snd_ctl_elem_value *uctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct soc_enum *e = (struct soc_enum *)kctl->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int reg, i, bit_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Find the bit position of current MUX input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * If nothing is set, position would be 0 and it corresponds to 'None'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) for (i = 0; i < ahub->soc_data->reg_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) reg = e->reg + (TEGRA210_XBAR_PART1_RX * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) reg_val = snd_soc_component_read(cmpnt, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) reg_val &= ahub->soc_data->mask[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (reg_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) bit_pos = ffs(reg_val) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) (8 * cmpnt->val_bytes * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Find index related to the item in array *_ahub_mux_texts[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) for (i = 0; i < e->items; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (bit_pos == e->values[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) uctl->value.enumerated.item[0] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int tegra_ahub_put_value_enum(struct snd_kcontrol *kctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct snd_ctl_elem_value *uctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct soc_enum *e = (struct soc_enum *)kctl->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct snd_soc_dapm_update update[TEGRA_XBAR_UPDATE_MAX_REG] = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int *item = uctl->value.enumerated.item;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int value = e->values[item[0]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int i, bit_pos, reg_idx = 0, reg_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (item[0] >= e->items)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Get the register index and value to set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg_idx = (value - 1) / (8 * cmpnt->val_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) bit_pos = (value - 1) % (8 * cmpnt->val_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg_val = BIT(bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Run through all parts of a MUX register to find the state changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * There will be an additional update if new MUX input value is from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * different part of the MUX register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) for (i = 0; i < ahub->soc_data->reg_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) update[i].reg = e->reg + (TEGRA210_XBAR_PART1_RX * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) update[i].val = (i == reg_idx) ? reg_val : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) update[i].mask = ahub->soc_data->mask[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) update[i].kcontrol = kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Update widget power if state has changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (snd_soc_component_test_bits(cmpnt, update[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) update[i].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) update[i].val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) change |= snd_soc_dapm_mux_update_power(dapm, kctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) item[0], e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) &update[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct snd_soc_dai_driver tegra210_ahub_dais[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DAI(ADMAIF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DAI(ADMAIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DAI(ADMAIF3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DAI(ADMAIF4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DAI(ADMAIF5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DAI(ADMAIF6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DAI(ADMAIF7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DAI(ADMAIF8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DAI(ADMAIF9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DAI(ADMAIF10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DAI(I2S1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DAI(I2S2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DAI(I2S3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DAI(I2S4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DAI(I2S5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DAI(DMIC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DAI(DMIC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DAI(DMIC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct snd_soc_dai_driver tegra186_ahub_dais[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DAI(ADMAIF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DAI(ADMAIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DAI(ADMAIF3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DAI(ADMAIF4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DAI(ADMAIF5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DAI(ADMAIF6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DAI(ADMAIF7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DAI(ADMAIF8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DAI(ADMAIF9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DAI(ADMAIF10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DAI(ADMAIF11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DAI(ADMAIF12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DAI(ADMAIF13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DAI(ADMAIF14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DAI(ADMAIF15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DAI(ADMAIF16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DAI(ADMAIF17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DAI(ADMAIF18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DAI(ADMAIF19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DAI(ADMAIF20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DAI(I2S1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DAI(I2S2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DAI(I2S3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DAI(I2S4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DAI(I2S5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DAI(I2S6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DAI(DMIC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DAI(DMIC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DAI(DMIC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DAI(DMIC4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DAI(DSPK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DAI(DSPK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const char * const tegra210_ahub_mux_texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "None",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "ADMAIF1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "ADMAIF2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "ADMAIF3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "ADMAIF4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "ADMAIF5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "ADMAIF6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "ADMAIF7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "ADMAIF8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "ADMAIF9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "ADMAIF10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "I2S1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "I2S2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "I2S3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "I2S4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "I2S5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "DMIC1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "DMIC2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "DMIC3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const char * const tegra186_ahub_mux_texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "None",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "ADMAIF1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "ADMAIF2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "ADMAIF3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "ADMAIF4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "ADMAIF5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "ADMAIF6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "ADMAIF7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "ADMAIF8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "ADMAIF9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "ADMAIF10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "ADMAIF11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "ADMAIF12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "ADMAIF13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "ADMAIF14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "ADMAIF15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "ADMAIF16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "I2S1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "I2S2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "I2S3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "I2S4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "I2S5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "I2S6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "ADMAIF17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "ADMAIF18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "ADMAIF19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "ADMAIF20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "DMIC1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "DMIC2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "DMIC3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "DMIC4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const unsigned int tegra210_ahub_mux_values[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MUX_VALUE(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MUX_VALUE(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MUX_VALUE(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MUX_VALUE(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MUX_VALUE(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MUX_VALUE(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MUX_VALUE(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MUX_VALUE(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MUX_VALUE(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MUX_VALUE(0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MUX_VALUE(0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MUX_VALUE(0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MUX_VALUE(0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MUX_VALUE(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MUX_VALUE(0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MUX_VALUE(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MUX_VALUE(2, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MUX_VALUE(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const unsigned int tegra186_ahub_mux_values[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MUX_VALUE(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MUX_VALUE(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MUX_VALUE(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MUX_VALUE(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MUX_VALUE(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MUX_VALUE(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MUX_VALUE(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MUX_VALUE(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MUX_VALUE(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MUX_VALUE(0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MUX_VALUE(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MUX_VALUE(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MUX_VALUE(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MUX_VALUE(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MUX_VALUE(0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MUX_VALUE(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MUX_VALUE(0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MUX_VALUE(0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MUX_VALUE(0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MUX_VALUE(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MUX_VALUE(0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MUX_VALUE(0, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MUX_VALUE(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MUX_VALUE(3, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MUX_VALUE(3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MUX_VALUE(3, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MUX_VALUE(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MUX_VALUE(2, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MUX_VALUE(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MUX_VALUE(2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Controls for t210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MUX_ENUM_CTRL_DECL(t210_admaif1_tx, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MUX_ENUM_CTRL_DECL(t210_admaif2_tx, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MUX_ENUM_CTRL_DECL(t210_admaif3_tx, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MUX_ENUM_CTRL_DECL(t210_admaif4_tx, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MUX_ENUM_CTRL_DECL(t210_admaif5_tx, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MUX_ENUM_CTRL_DECL(t210_admaif6_tx, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MUX_ENUM_CTRL_DECL(t210_admaif7_tx, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MUX_ENUM_CTRL_DECL(t210_admaif8_tx, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MUX_ENUM_CTRL_DECL(t210_admaif9_tx, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MUX_ENUM_CTRL_DECL(t210_admaif10_tx, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MUX_ENUM_CTRL_DECL(t210_i2s1_tx, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MUX_ENUM_CTRL_DECL(t210_i2s2_tx, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MUX_ENUM_CTRL_DECL(t210_i2s3_tx, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MUX_ENUM_CTRL_DECL(t210_i2s4_tx, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MUX_ENUM_CTRL_DECL(t210_i2s5_tx, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Controls for t186 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MUX_ENUM_CTRL_DECL_186(t186_admaif2_tx, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MUX_ENUM_CTRL_DECL_186(t186_admaif3_tx, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MUX_ENUM_CTRL_DECL_186(t186_admaif4_tx, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MUX_ENUM_CTRL_DECL_186(t186_admaif5_tx, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MUX_ENUM_CTRL_DECL_186(t186_admaif6_tx, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MUX_ENUM_CTRL_DECL_186(t186_admaif7_tx, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MUX_ENUM_CTRL_DECL_186(t186_admaif8_tx, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MUX_ENUM_CTRL_DECL_186(t186_admaif9_tx, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MUX_ENUM_CTRL_DECL_186(t186_admaif10_tx, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MUX_ENUM_CTRL_DECL_186(t186_i2s1_tx, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MUX_ENUM_CTRL_DECL_186(t186_i2s2_tx, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MUX_ENUM_CTRL_DECL_186(t186_i2s3_tx, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MUX_ENUM_CTRL_DECL_186(t186_i2s4_tx, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MUX_ENUM_CTRL_DECL_186(t186_i2s5_tx, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MUX_ENUM_CTRL_DECL_186(t186_admaif11_tx, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MUX_ENUM_CTRL_DECL_186(t186_admaif12_tx, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MUX_ENUM_CTRL_DECL_186(t186_admaif13_tx, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MUX_ENUM_CTRL_DECL_186(t186_admaif14_tx, 0x0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MUX_ENUM_CTRL_DECL_186(t186_admaif15_tx, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MUX_ENUM_CTRL_DECL_186(t186_admaif16_tx, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MUX_ENUM_CTRL_DECL_186(t186_i2s6_tx, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MUX_ENUM_CTRL_DECL_186(t186_dspk1_tx, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MUX_ENUM_CTRL_DECL_186(t186_dspk2_tx, 0x31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MUX_ENUM_CTRL_DECL_186(t186_admaif17_tx, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MUX_ENUM_CTRL_DECL_186(t186_admaif18_tx, 0x69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MUX_ENUM_CTRL_DECL_186(t186_admaif19_tx, 0x6a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MUX_ENUM_CTRL_DECL_186(t186_admaif20_tx, 0x6b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * The number of entries in, and order of, this array is closely tied to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * calculation of tegra210_ahub_codec.num_dapm_widgets near the end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * tegra210_ahub_probe()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) WIDGETS("ADMAIF1", t210_admaif1_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) WIDGETS("ADMAIF2", t210_admaif2_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) WIDGETS("ADMAIF3", t210_admaif3_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) WIDGETS("ADMAIF4", t210_admaif4_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) WIDGETS("ADMAIF5", t210_admaif5_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) WIDGETS("ADMAIF6", t210_admaif6_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) WIDGETS("ADMAIF7", t210_admaif7_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) WIDGETS("ADMAIF8", t210_admaif8_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) WIDGETS("ADMAIF9", t210_admaif9_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) WIDGETS("ADMAIF10", t210_admaif10_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) WIDGETS("I2S1", t210_i2s1_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) WIDGETS("I2S2", t210_i2s2_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) WIDGETS("I2S3", t210_i2s3_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) WIDGETS("I2S4", t210_i2s4_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) WIDGETS("I2S5", t210_i2s5_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) TX_WIDGETS("DMIC1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) TX_WIDGETS("DMIC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) TX_WIDGETS("DMIC3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) WIDGETS("ADMAIF1", t186_admaif1_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) WIDGETS("ADMAIF2", t186_admaif2_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) WIDGETS("ADMAIF3", t186_admaif3_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) WIDGETS("ADMAIF4", t186_admaif4_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) WIDGETS("ADMAIF5", t186_admaif5_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) WIDGETS("ADMAIF6", t186_admaif6_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) WIDGETS("ADMAIF7", t186_admaif7_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) WIDGETS("ADMAIF8", t186_admaif8_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) WIDGETS("ADMAIF9", t186_admaif9_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) WIDGETS("ADMAIF10", t186_admaif10_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) WIDGETS("ADMAIF11", t186_admaif11_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) WIDGETS("ADMAIF12", t186_admaif12_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) WIDGETS("ADMAIF13", t186_admaif13_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) WIDGETS("ADMAIF14", t186_admaif14_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) WIDGETS("ADMAIF15", t186_admaif15_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) WIDGETS("ADMAIF16", t186_admaif16_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) WIDGETS("ADMAIF17", t186_admaif17_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) WIDGETS("ADMAIF18", t186_admaif18_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) WIDGETS("ADMAIF19", t186_admaif19_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) WIDGETS("ADMAIF20", t186_admaif20_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) WIDGETS("I2S1", t186_i2s1_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) WIDGETS("I2S2", t186_i2s2_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) WIDGETS("I2S3", t186_i2s3_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) WIDGETS("I2S4", t186_i2s4_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) WIDGETS("I2S5", t186_i2s5_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) WIDGETS("I2S6", t186_i2s6_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) TX_WIDGETS("DMIC1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) TX_WIDGETS("DMIC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) TX_WIDGETS("DMIC3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) TX_WIDGETS("DMIC4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) WIDGETS("DSPK1", t186_dspk1_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) WIDGETS("DSPK2", t186_dspk2_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define TEGRA_COMMON_MUX_ROUTES(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { name " XBAR-TX", NULL, name " Mux" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { name " Mux", "ADMAIF1", "ADMAIF1 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { name " Mux", "ADMAIF2", "ADMAIF2 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { name " Mux", "ADMAIF3", "ADMAIF3 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { name " Mux", "ADMAIF4", "ADMAIF4 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { name " Mux", "ADMAIF5", "ADMAIF5 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { name " Mux", "ADMAIF6", "ADMAIF6 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { name " Mux", "ADMAIF7", "ADMAIF7 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { name " Mux", "ADMAIF8", "ADMAIF8 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { name " Mux", "ADMAIF9", "ADMAIF9 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { name " Mux", "ADMAIF10", "ADMAIF10 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { name " Mux", "I2S1", "I2S1 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { name " Mux", "I2S2", "I2S2 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { name " Mux", "I2S3", "I2S3 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { name " Mux", "I2S4", "I2S4 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { name " Mux", "I2S5", "I2S5 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { name " Mux", "DMIC1", "DMIC1 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { name " Mux", "DMIC2", "DMIC2 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { name " Mux", "DMIC3", "DMIC3 XBAR-RX" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TEGRA186_ONLY_MUX_ROUTES(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { name " Mux", "ADMAIF11", "ADMAIF11 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { name " Mux", "ADMAIF12", "ADMAIF12 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { name " Mux", "ADMAIF13", "ADMAIF13 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { name " Mux", "ADMAIF14", "ADMAIF14 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { name " Mux", "ADMAIF15", "ADMAIF15 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { name " Mux", "ADMAIF16", "ADMAIF16 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { name " Mux", "ADMAIF17", "ADMAIF17 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { name " Mux", "ADMAIF18", "ADMAIF18 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { name " Mux", "ADMAIF19", "ADMAIF19 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { name " Mux", "ADMAIF20", "ADMAIF20 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { name " Mux", "I2S6", "I2S6 XBAR-RX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { name " Mux", "DMIC4", "DMIC4 XBAR-RX" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define TEGRA210_MUX_ROUTES(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) TEGRA_COMMON_MUX_ROUTES(name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define TEGRA186_MUX_ROUTES(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) TEGRA_COMMON_MUX_ROUTES(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) TEGRA186_ONLY_MUX_ROUTES(name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Connect FEs with XBAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define TEGRA_FE_ROUTES(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { name " XBAR-Playback", NULL, name " Playback" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { name " XBAR-RX", NULL, name " XBAR-Playback"}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { name " XBAR-Capture", NULL, name " XBAR-TX" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { name " Capture", NULL, name " XBAR-Capture" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * The number of entries in, and order of, this array is closely tied to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * calculation of tegra210_ahub_codec.num_dapm_routes near the end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * tegra210_ahub_probe()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const struct snd_soc_dapm_route tegra210_ahub_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) TEGRA_FE_ROUTES("ADMAIF1")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) TEGRA_FE_ROUTES("ADMAIF2")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) TEGRA_FE_ROUTES("ADMAIF3")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) TEGRA_FE_ROUTES("ADMAIF4")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) TEGRA_FE_ROUTES("ADMAIF5")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) TEGRA_FE_ROUTES("ADMAIF6")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) TEGRA_FE_ROUTES("ADMAIF7")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) TEGRA_FE_ROUTES("ADMAIF8")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) TEGRA_FE_ROUTES("ADMAIF9")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) TEGRA_FE_ROUTES("ADMAIF10")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) TEGRA210_MUX_ROUTES("ADMAIF1")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) TEGRA210_MUX_ROUTES("ADMAIF2")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) TEGRA210_MUX_ROUTES("ADMAIF3")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) TEGRA210_MUX_ROUTES("ADMAIF4")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) TEGRA210_MUX_ROUTES("ADMAIF5")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) TEGRA210_MUX_ROUTES("ADMAIF6")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) TEGRA210_MUX_ROUTES("ADMAIF7")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) TEGRA210_MUX_ROUTES("ADMAIF8")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) TEGRA210_MUX_ROUTES("ADMAIF9")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) TEGRA210_MUX_ROUTES("ADMAIF10")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) TEGRA210_MUX_ROUTES("I2S1")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) TEGRA210_MUX_ROUTES("I2S2")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) TEGRA210_MUX_ROUTES("I2S3")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) TEGRA210_MUX_ROUTES("I2S4")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) TEGRA210_MUX_ROUTES("I2S5")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct snd_soc_dapm_route tegra186_ahub_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) TEGRA_FE_ROUTES("ADMAIF1")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) TEGRA_FE_ROUTES("ADMAIF2")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) TEGRA_FE_ROUTES("ADMAIF3")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) TEGRA_FE_ROUTES("ADMAIF4")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) TEGRA_FE_ROUTES("ADMAIF5")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) TEGRA_FE_ROUTES("ADMAIF6")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) TEGRA_FE_ROUTES("ADMAIF7")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) TEGRA_FE_ROUTES("ADMAIF8")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) TEGRA_FE_ROUTES("ADMAIF9")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) TEGRA_FE_ROUTES("ADMAIF10")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) TEGRA_FE_ROUTES("ADMAIF11")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) TEGRA_FE_ROUTES("ADMAIF12")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) TEGRA_FE_ROUTES("ADMAIF13")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) TEGRA_FE_ROUTES("ADMAIF14")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) TEGRA_FE_ROUTES("ADMAIF15")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) TEGRA_FE_ROUTES("ADMAIF16")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) TEGRA_FE_ROUTES("ADMAIF17")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) TEGRA_FE_ROUTES("ADMAIF18")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) TEGRA_FE_ROUTES("ADMAIF19")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) TEGRA_FE_ROUTES("ADMAIF20")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) TEGRA186_MUX_ROUTES("ADMAIF1")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) TEGRA186_MUX_ROUTES("ADMAIF2")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) TEGRA186_MUX_ROUTES("ADMAIF3")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) TEGRA186_MUX_ROUTES("ADMAIF4")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) TEGRA186_MUX_ROUTES("ADMAIF5")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) TEGRA186_MUX_ROUTES("ADMAIF6")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) TEGRA186_MUX_ROUTES("ADMAIF7")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) TEGRA186_MUX_ROUTES("ADMAIF8")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) TEGRA186_MUX_ROUTES("ADMAIF9")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) TEGRA186_MUX_ROUTES("ADMAIF10")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) TEGRA186_MUX_ROUTES("ADMAIF11")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) TEGRA186_MUX_ROUTES("ADMAIF12")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) TEGRA186_MUX_ROUTES("ADMAIF13")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) TEGRA186_MUX_ROUTES("ADMAIF14")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) TEGRA186_MUX_ROUTES("ADMAIF15")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) TEGRA186_MUX_ROUTES("ADMAIF16")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) TEGRA186_MUX_ROUTES("ADMAIF17")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) TEGRA186_MUX_ROUTES("ADMAIF18")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) TEGRA186_MUX_ROUTES("ADMAIF19")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) TEGRA186_MUX_ROUTES("ADMAIF20")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) TEGRA186_MUX_ROUTES("I2S1")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) TEGRA186_MUX_ROUTES("I2S2")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) TEGRA186_MUX_ROUTES("I2S3")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) TEGRA186_MUX_ROUTES("I2S4")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) TEGRA186_MUX_ROUTES("I2S5")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) TEGRA186_MUX_ROUTES("I2S6")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) TEGRA186_MUX_ROUTES("DSPK1")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) TEGRA186_MUX_ROUTES("DSPK2")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static const struct snd_soc_component_driver tegra210_ahub_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .dapm_widgets = tegra210_ahub_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .num_dapm_widgets = ARRAY_SIZE(tegra210_ahub_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .dapm_routes = tegra210_ahub_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .num_dapm_routes = ARRAY_SIZE(tegra210_ahub_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct snd_soc_component_driver tegra186_ahub_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .dapm_widgets = tegra186_ahub_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .num_dapm_widgets = ARRAY_SIZE(tegra186_ahub_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .dapm_routes = tegra186_ahub_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct regmap_config tegra210_ahub_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .max_register = TEGRA210_MAX_REGISTER_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const struct regmap_config tegra186_ahub_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .max_register = TEGRA186_MAX_REGISTER_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct tegra_ahub_soc_data soc_data_tegra210 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .cmpnt_drv = &tegra210_ahub_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .dai_drv = tegra210_ahub_dais,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .num_dais = ARRAY_SIZE(tegra210_ahub_dais),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .regmap_config = &tegra210_ahub_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .mask[0] = TEGRA210_XBAR_REG_MASK_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .mask[1] = TEGRA210_XBAR_REG_MASK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .mask[2] = TEGRA210_XBAR_REG_MASK_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .mask[3] = TEGRA210_XBAR_REG_MASK_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .reg_count = TEGRA210_XBAR_UPDATE_MAX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const struct tegra_ahub_soc_data soc_data_tegra186 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .cmpnt_drv = &tegra186_ahub_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .dai_drv = tegra186_ahub_dais,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .num_dais = ARRAY_SIZE(tegra186_ahub_dais),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .regmap_config = &tegra186_ahub_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .mask[0] = TEGRA186_XBAR_REG_MASK_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .mask[1] = TEGRA186_XBAR_REG_MASK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .mask[2] = TEGRA186_XBAR_REG_MASK_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .mask[3] = TEGRA186_XBAR_REG_MASK_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const struct of_device_id tegra_ahub_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { .compatible = "nvidia,tegra186-ahub", .data = &soc_data_tegra186 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_DEVICE_TABLE(of, tegra_ahub_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int __maybe_unused tegra_ahub_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct tegra_ahub *ahub = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) regcache_cache_only(ahub->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) regcache_mark_dirty(ahub->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) clk_disable_unprepare(ahub->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int __maybe_unused tegra_ahub_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct tegra_ahub *ahub = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) err = clk_prepare_enable(ahub->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_err(dev, "failed to enable AHUB clock, err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) regcache_cache_only(ahub->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) regcache_sync(ahub->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int tegra_ahub_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct tegra_ahub *ahub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ahub = devm_kzalloc(&pdev->dev, sizeof(*ahub), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (!ahub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ahub->soc_data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) platform_set_drvdata(pdev, ahub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ahub->clk = devm_clk_get(&pdev->dev, "ahub");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (IS_ERR(ahub->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dev_err(&pdev->dev, "can't retrieve AHUB clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return PTR_ERR(ahub->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ahub->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ahub->soc_data->regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (IS_ERR(ahub->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_err(&pdev->dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return PTR_ERR(ahub->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) regcache_cache_only(ahub->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) err = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ahub->soc_data->cmpnt_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ahub->soc_data->dai_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ahub->soc_data->num_dais);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dev_err(&pdev->dev, "can't register AHUB component, err: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int tegra_ahub_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static const struct dev_pm_ops tegra_ahub_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) SET_RUNTIME_PM_OPS(tegra_ahub_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) tegra_ahub_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static struct platform_driver tegra_ahub_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .probe = tegra_ahub_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .remove = tegra_ahub_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .name = "tegra210-ahub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .of_match_table = tegra_ahub_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .pm = &tegra_ahub_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) module_platform_driver(tegra_ahub_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) MODULE_DESCRIPTION("Tegra210 ASoC AHUB driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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