^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tegra210_admaif.h - Tegra ADMAIF registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __TEGRA_ADMAIF_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __TEGRA_ADMAIF_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TEGRA_ADMAIF_CHANNEL_REG_STRIDE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Tegra210 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA210_ADMAIF_LAST_REG 0x75f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA210_ADMAIF_CHANNEL_COUNT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA210_ADMAIF_RX_BASE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA210_ADMAIF_TX_BASE 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA210_ADMAIF_GLOBAL_BASE 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Tegra186 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA186_ADMAIF_LAST_REG 0xd5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA186_ADMAIF_CHANNEL_COUNT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA186_ADMAIF_RX_BASE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA186_ADMAIF_TX_BASE 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA186_ADMAIF_GLOBAL_BASE 0xd00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Global registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA_ADMAIF_GLOBAL_ENABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA_ADMAIF_GLOBAL_CG_0 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA_ADMAIF_GLOBAL_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* RX channel registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA_ADMAIF_RX_ENABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA_ADMAIF_RX_SOFT_RESET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA_ADMAIF_RX_STATUS 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA_ADMAIF_RX_INT_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA_ADMAIF_RX_INT_MASK 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA_ADMAIF_RX_INT_SET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA_ADMAIF_RX_INT_CLEAR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA_ADMAIF_CH_ACIF_RX_CTRL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA_ADMAIF_RX_FIFO_CTRL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA_ADMAIF_RX_FIFO_READ 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* TX channel registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA_ADMAIF_TX_ENABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA_ADMAIF_TX_SOFT_RESET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA_ADMAIF_TX_STATUS 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA_ADMAIF_TX_INT_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA_ADMAIF_TX_INT_MASK 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA_ADMAIF_TX_INT_SET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA_ADMAIF_TX_INT_CLEAR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEGRA_ADMAIF_CH_ACIF_TX_CTRL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TEGRA_ADMAIF_TX_FIFO_CTRL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA_ADMAIF_TX_FIFO_WRITE 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PACK8_EN_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PACK8_EN_MASK BIT(PACK8_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PACK8_EN BIT(PACK8_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PACK16_EN_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PACK16_EN_MASK BIT(PACK16_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PACK16_EN BIT(PACK16_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TX_ENABLE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TX_ENABLE_MASK BIT(TX_ENABLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TX_ENABLE BIT(TX_ENABLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RX_ENABLE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RX_ENABLE_MASK BIT(RX_ENABLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RX_ENABLE BIT(RX_ENABLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SW_RESET_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SW_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Default values - Tegra210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA210_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA210_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TEGRA210_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TEGRA210_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000020b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA210_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x0000020e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEGRA210_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TEGRA210_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEGRA210_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TEGRA210_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TEGRA210_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TEGRA210_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TEGRA210_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TEGRA210_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x01800208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TEGRA210_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0180020b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TEGRA210_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x0180020e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TEGRA210_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TEGRA210_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TEGRA210_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TEGRA210_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TEGRA210_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Default values - Tegra186 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TEGRA186_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TEGRA186_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TEGRA186_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TEGRA186_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TEGRA186_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x00000210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TEGRA186_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TEGRA186_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TEGRA186_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TEGRA186_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TEGRA186_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA186_ADMAIF_RX11_FIFO_CTRL_REG_DEFAULT 0x00000222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA186_ADMAIF_RX12_FIFO_CTRL_REG_DEFAULT 0x00000225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA186_ADMAIF_RX13_FIFO_CTRL_REG_DEFAULT 0x00000228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA186_ADMAIF_RX14_FIFO_CTRL_REG_DEFAULT 0x0000022b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA186_ADMAIF_RX15_FIFO_CTRL_REG_DEFAULT 0x0000022e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TEGRA186_ADMAIF_RX16_FIFO_CTRL_REG_DEFAULT 0x00000231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA186_ADMAIF_RX17_FIFO_CTRL_REG_DEFAULT 0x00000234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA186_ADMAIF_RX18_FIFO_CTRL_REG_DEFAULT 0x00000237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA186_ADMAIF_RX19_FIFO_CTRL_REG_DEFAULT 0x0000023a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA186_ADMAIF_RX20_FIFO_CTRL_REG_DEFAULT 0x0000023d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA186_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA186_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA186_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x02000308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA186_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0200030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA186_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x01800210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA186_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA186_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TEGRA186_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TEGRA186_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TEGRA186_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TEGRA186_ADMAIF_TX11_FIFO_CTRL_REG_DEFAULT 0x01800222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TEGRA186_ADMAIF_TX12_FIFO_CTRL_REG_DEFAULT 0x01800225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA186_ADMAIF_TX13_FIFO_CTRL_REG_DEFAULT 0x01800228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA186_ADMAIF_TX14_FIFO_CTRL_REG_DEFAULT 0x0180022b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA186_ADMAIF_TX15_FIFO_CTRL_REG_DEFAULT 0x0180022e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA186_ADMAIF_TX16_FIFO_CTRL_REG_DEFAULT 0x01800231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA186_ADMAIF_TX17_FIFO_CTRL_REG_DEFAULT 0x01800234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA186_ADMAIF_TX18_FIFO_CTRL_REG_DEFAULT 0x01800237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA186_ADMAIF_TX19_FIFO_CTRL_REG_DEFAULT 0x0180023a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA186_ADMAIF_TX20_FIFO_CTRL_REG_DEFAULT 0x0180023d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DATA_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DATA_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DATA_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ADMAIF_RX_PATH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ADMAIF_TX_PATH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ADMAIF_PATHS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct tegra_admaif_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const struct snd_soc_component_driver *cmpnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const struct regmap_config *regmap_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct snd_soc_dai_driver *dais;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int global_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int tx_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int rx_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int num_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct tegra_admaif {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct snd_dmaengine_dai_dma_data *capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct snd_dmaengine_dai_dma_data *playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const struct tegra_admaif_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int *mono_to_stereo[ADMAIF_PATHS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int *stereo_to_mono[ADMAIF_PATHS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags