^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // tegra210_admaif.c - Tegra ADMAIF driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "tegra210_admaif.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "tegra_cif.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "tegra_pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CH_REG(offset, reg, id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ((offset) + (reg) + (TEGRA_ADMAIF_CHANNEL_REG_STRIDE * (id)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CH_TX_REG(reg, id) CH_REG(admaif->soc_data->tx_base, reg, id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CH_RX_REG(reg, id) CH_REG(admaif->soc_data->rx_base, reg, id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_DEFAULTS(id, rx_ctrl, tx_ctrl, tx_base, rx_base) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { CH_REG(rx_base, TEGRA_ADMAIF_RX_INT_MASK, id), 0x00000001 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { CH_REG(rx_base, TEGRA_ADMAIF_CH_ACIF_RX_CTRL, id), 0x00007700 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { CH_REG(rx_base, TEGRA_ADMAIF_RX_FIFO_CTRL, id), rx_ctrl }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { CH_REG(tx_base, TEGRA_ADMAIF_TX_INT_MASK, id), 0x00000001 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { CH_REG(tx_base, TEGRA_ADMAIF_CH_ACIF_TX_CTRL, id), 0x00007700 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { CH_REG(tx_base, TEGRA_ADMAIF_TX_FIFO_CTRL, id), tx_ctrl }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADMAIF_REG_DEFAULTS(id, chip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) REG_DEFAULTS((id) - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) chip ## _ADMAIF_RX ## id ## _FIFO_CTRL_REG_DEFAULT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) chip ## _ADMAIF_TX ## id ## _FIFO_CTRL_REG_DEFAULT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) chip ## _ADMAIF_TX_BASE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) chip ## _ADMAIF_RX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const struct reg_default tegra186_admaif_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA186_ADMAIF_GLOBAL_BASE), 0x00000003},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ADMAIF_REG_DEFAULTS(1, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ADMAIF_REG_DEFAULTS(2, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ADMAIF_REG_DEFAULTS(3, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ADMAIF_REG_DEFAULTS(4, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ADMAIF_REG_DEFAULTS(5, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ADMAIF_REG_DEFAULTS(6, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ADMAIF_REG_DEFAULTS(7, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ADMAIF_REG_DEFAULTS(8, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ADMAIF_REG_DEFAULTS(9, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ADMAIF_REG_DEFAULTS(10, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ADMAIF_REG_DEFAULTS(11, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ADMAIF_REG_DEFAULTS(12, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ADMAIF_REG_DEFAULTS(13, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ADMAIF_REG_DEFAULTS(14, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ADMAIF_REG_DEFAULTS(15, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ADMAIF_REG_DEFAULTS(16, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ADMAIF_REG_DEFAULTS(17, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ADMAIF_REG_DEFAULTS(18, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ADMAIF_REG_DEFAULTS(19, TEGRA186),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ADMAIF_REG_DEFAULTS(20, TEGRA186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct reg_default tegra210_admaif_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA210_ADMAIF_GLOBAL_BASE), 0x00000003},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ADMAIF_REG_DEFAULTS(1, TEGRA210),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ADMAIF_REG_DEFAULTS(2, TEGRA210),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ADMAIF_REG_DEFAULTS(3, TEGRA210),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ADMAIF_REG_DEFAULTS(4, TEGRA210),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ADMAIF_REG_DEFAULTS(5, TEGRA210),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ADMAIF_REG_DEFAULTS(6, TEGRA210),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ADMAIF_REG_DEFAULTS(7, TEGRA210),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ADMAIF_REG_DEFAULTS(8, TEGRA210),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ADMAIF_REG_DEFAULTS(9, TEGRA210),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ADMAIF_REG_DEFAULTS(10, TEGRA210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static bool tegra_admaif_wr_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct tegra_admaif *admaif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int ch_stride = TEGRA_ADMAIF_CHANNEL_REG_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int num_ch = admaif->soc_data->num_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int rx_base = admaif->soc_data->rx_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int tx_base = admaif->soc_data->tx_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int global_base = admaif->soc_data->global_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int reg_max = admaif->soc_data->regmap_conf->max_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int rx_max = rx_base + (num_ch * ch_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int tx_max = tx_base + (num_ch * ch_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if ((reg >= rx_base) && (reg < rx_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) reg = (reg - rx_base) % ch_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if ((reg == TEGRA_ADMAIF_RX_ENABLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (reg == TEGRA_ADMAIF_RX_FIFO_CTRL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (reg == TEGRA_ADMAIF_RX_SOFT_RESET) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (reg == TEGRA_ADMAIF_CH_ACIF_RX_CTRL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } else if ((reg >= tx_base) && (reg < tx_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) reg = (reg - tx_base) % ch_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if ((reg == TEGRA_ADMAIF_TX_ENABLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (reg == TEGRA_ADMAIF_TX_FIFO_CTRL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) (reg == TEGRA_ADMAIF_TX_SOFT_RESET) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) (reg == TEGRA_ADMAIF_CH_ACIF_TX_CTRL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } else if ((reg >= global_base) && (reg < reg_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (reg == (global_base + TEGRA_ADMAIF_GLOBAL_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static bool tegra_admaif_rd_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct tegra_admaif *admaif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int ch_stride = TEGRA_ADMAIF_CHANNEL_REG_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int num_ch = admaif->soc_data->num_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int rx_base = admaif->soc_data->rx_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int tx_base = admaif->soc_data->tx_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int global_base = admaif->soc_data->global_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int reg_max = admaif->soc_data->regmap_conf->max_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int rx_max = rx_base + (num_ch * ch_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int tx_max = tx_base + (num_ch * ch_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if ((reg >= rx_base) && (reg < rx_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg = (reg - rx_base) % ch_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if ((reg == TEGRA_ADMAIF_RX_ENABLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) (reg == TEGRA_ADMAIF_RX_STATUS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) (reg == TEGRA_ADMAIF_RX_INT_STATUS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (reg == TEGRA_ADMAIF_RX_FIFO_CTRL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) (reg == TEGRA_ADMAIF_RX_SOFT_RESET) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) (reg == TEGRA_ADMAIF_CH_ACIF_RX_CTRL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) } else if ((reg >= tx_base) && (reg < tx_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) reg = (reg - tx_base) % ch_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if ((reg == TEGRA_ADMAIF_TX_ENABLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (reg == TEGRA_ADMAIF_TX_STATUS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (reg == TEGRA_ADMAIF_TX_INT_STATUS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) (reg == TEGRA_ADMAIF_TX_FIFO_CTRL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) (reg == TEGRA_ADMAIF_TX_SOFT_RESET) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (reg == TEGRA_ADMAIF_CH_ACIF_TX_CTRL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) } else if ((reg >= global_base) && (reg < reg_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if ((reg == (global_base + TEGRA_ADMAIF_GLOBAL_ENABLE)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) (reg == (global_base + TEGRA_ADMAIF_GLOBAL_CG_0)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) (reg == (global_base + TEGRA_ADMAIF_GLOBAL_STATUS)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) (reg == (global_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) (reg == (global_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static bool tegra_admaif_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct tegra_admaif *admaif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int ch_stride = TEGRA_ADMAIF_CHANNEL_REG_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int num_ch = admaif->soc_data->num_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int rx_base = admaif->soc_data->rx_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int tx_base = admaif->soc_data->tx_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int global_base = admaif->soc_data->global_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int reg_max = admaif->soc_data->regmap_conf->max_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int rx_max = rx_base + (num_ch * ch_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int tx_max = tx_base + (num_ch * ch_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if ((reg >= rx_base) && (reg < rx_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) reg = (reg - rx_base) % ch_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if ((reg == TEGRA_ADMAIF_RX_ENABLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) (reg == TEGRA_ADMAIF_RX_STATUS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) (reg == TEGRA_ADMAIF_RX_INT_STATUS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) (reg == TEGRA_ADMAIF_RX_SOFT_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) } else if ((reg >= tx_base) && (reg < tx_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) reg = (reg - tx_base) % ch_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if ((reg == TEGRA_ADMAIF_TX_ENABLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) (reg == TEGRA_ADMAIF_TX_STATUS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) (reg == TEGRA_ADMAIF_TX_INT_STATUS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) (reg == TEGRA_ADMAIF_TX_SOFT_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } else if ((reg >= global_base) && (reg < reg_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if ((reg == (global_base + TEGRA_ADMAIF_GLOBAL_STATUS)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) (reg == (global_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) (reg == (global_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct regmap_config tegra210_admaif_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .max_register = TEGRA210_ADMAIF_LAST_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .writeable_reg = tegra_admaif_wr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .readable_reg = tegra_admaif_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .volatile_reg = tegra_admaif_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .reg_defaults = tegra210_admaif_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .num_reg_defaults = TEGRA210_ADMAIF_CHANNEL_COUNT * 6 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct regmap_config tegra186_admaif_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .max_register = TEGRA186_ADMAIF_LAST_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .writeable_reg = tegra_admaif_wr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .readable_reg = tegra_admaif_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .volatile_reg = tegra_admaif_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .reg_defaults = tegra186_admaif_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .num_reg_defaults = TEGRA186_ADMAIF_CHANNEL_COUNT * 6 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int __maybe_unused tegra_admaif_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct tegra_admaif *admaif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) regcache_cache_only(admaif->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) regcache_mark_dirty(admaif->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int __maybe_unused tegra_admaif_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct tegra_admaif *admaif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) regcache_cache_only(admaif->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) regcache_sync(admaif->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int tegra_admaif_set_pack_mode(struct regmap *map, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int valid_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) switch (valid_bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case DATA_8BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) regmap_update_bits(map, reg, PACK8_EN_MASK, PACK8_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) regmap_update_bits(map, reg, PACK16_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case DATA_16BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) regmap_update_bits(map, reg, PACK16_EN_MASK, PACK16_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) regmap_update_bits(map, reg, PACK8_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case DATA_32BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) regmap_update_bits(map, reg, PACK16_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) regmap_update_bits(map, reg, PACK8_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int tegra_admaif_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct device *dev = dai->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct tegra_admaif *admaif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct tegra_cif_conf cif_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int reg, path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int valid_bit, channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case SNDRV_PCM_FORMAT_S8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) cif_conf.audio_bits = TEGRA_ACIF_BITS_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) cif_conf.client_bits = TEGRA_ACIF_BITS_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) valid_bit = DATA_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) cif_conf.client_bits = TEGRA_ACIF_BITS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) valid_bit = DATA_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) cif_conf.client_bits = TEGRA_ACIF_BITS_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) valid_bit = DATA_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(dev, "unsupported format!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) cif_conf.client_ch = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) cif_conf.audio_ch = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) path = ADMAIF_TX_PATH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) reg = CH_TX_REG(TEGRA_ADMAIF_CH_ACIF_TX_CTRL, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) path = ADMAIF_RX_PATH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) reg = CH_RX_REG(TEGRA_ADMAIF_CH_ACIF_RX_CTRL, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) cif_conf.mono_conv = admaif->mono_to_stereo[path][dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) cif_conf.stereo_conv = admaif->stereo_to_mono[path][dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) tegra_admaif_set_pack_mode(admaif->regmap, reg, valid_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) tegra_set_cif(admaif->regmap, reg, &cif_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int tegra_admaif_start(struct snd_soc_dai *dai, int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct tegra_admaif *admaif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int reg, mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case SNDRV_PCM_STREAM_PLAYBACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mask = TX_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) val = TX_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) reg = CH_TX_REG(TEGRA_ADMAIF_TX_ENABLE, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case SNDRV_PCM_STREAM_CAPTURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mask = RX_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) val = RX_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) reg = CH_RX_REG(TEGRA_ADMAIF_RX_ENABLE, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) regmap_update_bits(admaif->regmap, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int tegra_admaif_stop(struct snd_soc_dai *dai, int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct tegra_admaif *admaif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned int enable_reg, status_reg, reset_reg, mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) char *dir_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int err, enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case SNDRV_PCM_STREAM_PLAYBACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mask = TX_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) enable = TX_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dir_name = "TX";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) enable_reg = CH_TX_REG(TEGRA_ADMAIF_TX_ENABLE, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) status_reg = CH_TX_REG(TEGRA_ADMAIF_TX_STATUS, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) reset_reg = CH_TX_REG(TEGRA_ADMAIF_TX_SOFT_RESET, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case SNDRV_PCM_STREAM_CAPTURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mask = RX_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) enable = RX_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dir_name = "RX";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) enable_reg = CH_RX_REG(TEGRA_ADMAIF_RX_ENABLE, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) status_reg = CH_RX_REG(TEGRA_ADMAIF_RX_STATUS, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) reset_reg = CH_RX_REG(TEGRA_ADMAIF_RX_SOFT_RESET, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Disable TX/RX channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) regmap_update_bits(admaif->regmap, enable_reg, mask, ~enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Wait until ADMAIF TX/RX status is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) err = regmap_read_poll_timeout_atomic(admaif->regmap, status_reg, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) !(val & enable), 10, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_warn(dai->dev, "timeout: failed to disable ADMAIF%d_%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dai->id + 1, dir_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* SW reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) regmap_update_bits(admaif->regmap, reset_reg, SW_RESET_MASK, SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Wait till SW reset is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) err = regmap_read_poll_timeout_atomic(admaif->regmap, reset_reg, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) !(val & SW_RESET_MASK & SW_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 10, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_err(dai->dev, "timeout: SW reset failed for ADMAIF%d_%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dai->id + 1, dir_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int tegra_admaif_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) err = snd_dmaengine_pcm_trigger(substream, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return tegra_admaif_start(dai, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return tegra_admaif_stop(dai, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const struct snd_soc_dai_ops tegra_admaif_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .hw_params = tegra_admaif_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .trigger = tegra_admaif_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int tegra210_admaif_pget_mono_to_stereo(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ucontrol->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) admaif->mono_to_stereo[ADMAIF_TX_PATH][ec->reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int tegra210_admaif_pput_mono_to_stereo(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (value == admaif->mono_to_stereo[ADMAIF_TX_PATH][ec->reg])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) admaif->mono_to_stereo[ADMAIF_TX_PATH][ec->reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int tegra210_admaif_cget_mono_to_stereo(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ucontrol->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) admaif->mono_to_stereo[ADMAIF_RX_PATH][ec->reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int tegra210_admaif_cput_mono_to_stereo(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (value == admaif->mono_to_stereo[ADMAIF_RX_PATH][ec->reg])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) admaif->mono_to_stereo[ADMAIF_RX_PATH][ec->reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int tegra210_admaif_pget_stereo_to_mono(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ucontrol->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) admaif->stereo_to_mono[ADMAIF_TX_PATH][ec->reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int tegra210_admaif_pput_stereo_to_mono(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (value == admaif->stereo_to_mono[ADMAIF_TX_PATH][ec->reg])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) admaif->stereo_to_mono[ADMAIF_TX_PATH][ec->reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int tegra210_admaif_cget_stereo_to_mono(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ucontrol->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) admaif->stereo_to_mono[ADMAIF_RX_PATH][ec->reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int tegra210_admaif_cput_stereo_to_mono(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct tegra_admaif *admaif = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct soc_enum *ec = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (value == admaif->stereo_to_mono[ADMAIF_RX_PATH][ec->reg])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) admaif->stereo_to_mono[ADMAIF_RX_PATH][ec->reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int tegra_admaif_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct tegra_admaif *admaif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dai->capture_dma_data = &admaif->capture_dma_data[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dai->playback_dma_data = &admaif->playback_dma_data[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define DAI(dai_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .name = dai_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .probe = tegra_admaif_dai_probe, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .playback = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .stream_name = dai_name " Playback", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .channels_min = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .channels_max = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .rates = SNDRV_PCM_RATE_8000_192000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .formats = SNDRV_PCM_FMTBIT_S8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) SNDRV_PCM_FMTBIT_S32_LE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .capture = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .stream_name = dai_name " Capture", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .channels_min = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .channels_max = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .rates = SNDRV_PCM_RATE_8000_192000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .formats = SNDRV_PCM_FMTBIT_S8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) SNDRV_PCM_FMTBIT_S32_LE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .ops = &tegra_admaif_dai_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static struct snd_soc_dai_driver tegra210_admaif_cmpnt_dais[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) DAI("ADMAIF1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) DAI("ADMAIF2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) DAI("ADMAIF3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) DAI("ADMAIF4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) DAI("ADMAIF5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) DAI("ADMAIF6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) DAI("ADMAIF7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) DAI("ADMAIF8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) DAI("ADMAIF9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) DAI("ADMAIF10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static struct snd_soc_dai_driver tegra186_admaif_cmpnt_dais[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) DAI("ADMAIF1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) DAI("ADMAIF2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) DAI("ADMAIF3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) DAI("ADMAIF4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) DAI("ADMAIF5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) DAI("ADMAIF6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) DAI("ADMAIF7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) DAI("ADMAIF8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) DAI("ADMAIF9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) DAI("ADMAIF10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) DAI("ADMAIF11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) DAI("ADMAIF12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) DAI("ADMAIF13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DAI("ADMAIF14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) DAI("ADMAIF15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) DAI("ADMAIF16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) DAI("ADMAIF17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) DAI("ADMAIF18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) DAI("ADMAIF19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) DAI("ADMAIF20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static const char * const tegra_admaif_stereo_conv_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) "CH0", "CH1", "AVG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static const char * const tegra_admaif_mono_conv_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) "Zero", "Copy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * Below macro is added to avoid looping over all ADMAIFx controls related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * to mono/stereo conversions in get()/put() callbacks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define NV_SOC_ENUM_EXT(xname, xreg, xhandler_get, xhandler_put, xenum_text) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .info = snd_soc_info_enum_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .get = xhandler_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .put = xhandler_put, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .private_value = (unsigned long)&(struct soc_enum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) SOC_ENUM_SINGLE(xreg, 0, ARRAY_SIZE(xenum_text), xenum_text) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define TEGRA_ADMAIF_CIF_CTRL(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) NV_SOC_ENUM_EXT("ADMAIF" #reg " Playback Mono To Stereo", reg - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) tegra210_admaif_pget_mono_to_stereo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) tegra210_admaif_pput_mono_to_stereo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) tegra_admaif_mono_conv_text), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) NV_SOC_ENUM_EXT("ADMAIF" #reg " Playback Stereo To Mono", reg - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) tegra210_admaif_pget_stereo_to_mono, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) tegra210_admaif_pput_stereo_to_mono, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) tegra_admaif_stereo_conv_text), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) NV_SOC_ENUM_EXT("ADMAIF" #reg " Capture Mono To Stereo", reg - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) tegra210_admaif_cget_mono_to_stereo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) tegra210_admaif_cput_mono_to_stereo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) tegra_admaif_mono_conv_text), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) NV_SOC_ENUM_EXT("ADMAIF" #reg " Capture Stereo To Mono", reg - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) tegra210_admaif_cget_stereo_to_mono, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) tegra210_admaif_cput_stereo_to_mono, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) tegra_admaif_stereo_conv_text)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static struct snd_kcontrol_new tegra210_admaif_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) TEGRA_ADMAIF_CIF_CTRL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) TEGRA_ADMAIF_CIF_CTRL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) TEGRA_ADMAIF_CIF_CTRL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) TEGRA_ADMAIF_CIF_CTRL(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) TEGRA_ADMAIF_CIF_CTRL(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) TEGRA_ADMAIF_CIF_CTRL(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) TEGRA_ADMAIF_CIF_CTRL(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) TEGRA_ADMAIF_CIF_CTRL(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) TEGRA_ADMAIF_CIF_CTRL(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) TEGRA_ADMAIF_CIF_CTRL(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static struct snd_kcontrol_new tegra186_admaif_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) TEGRA_ADMAIF_CIF_CTRL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) TEGRA_ADMAIF_CIF_CTRL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) TEGRA_ADMAIF_CIF_CTRL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) TEGRA_ADMAIF_CIF_CTRL(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) TEGRA_ADMAIF_CIF_CTRL(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) TEGRA_ADMAIF_CIF_CTRL(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) TEGRA_ADMAIF_CIF_CTRL(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) TEGRA_ADMAIF_CIF_CTRL(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) TEGRA_ADMAIF_CIF_CTRL(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) TEGRA_ADMAIF_CIF_CTRL(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) TEGRA_ADMAIF_CIF_CTRL(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) TEGRA_ADMAIF_CIF_CTRL(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) TEGRA_ADMAIF_CIF_CTRL(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) TEGRA_ADMAIF_CIF_CTRL(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) TEGRA_ADMAIF_CIF_CTRL(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) TEGRA_ADMAIF_CIF_CTRL(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) TEGRA_ADMAIF_CIF_CTRL(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) TEGRA_ADMAIF_CIF_CTRL(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) TEGRA_ADMAIF_CIF_CTRL(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) TEGRA_ADMAIF_CIF_CTRL(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const struct snd_soc_component_driver tegra210_admaif_cmpnt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .controls = tegra210_admaif_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .num_controls = ARRAY_SIZE(tegra210_admaif_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .pcm_construct = tegra_pcm_construct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .pcm_destruct = tegra_pcm_destruct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .open = tegra_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .close = tegra_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .hw_params = tegra_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .hw_free = tegra_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .mmap = tegra_pcm_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .pointer = tegra_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static const struct snd_soc_component_driver tegra186_admaif_cmpnt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .controls = tegra186_admaif_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .num_controls = ARRAY_SIZE(tegra186_admaif_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .pcm_construct = tegra_pcm_construct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .pcm_destruct = tegra_pcm_destruct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .open = tegra_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .close = tegra_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .hw_params = tegra_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .hw_free = tegra_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .mmap = tegra_pcm_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .pointer = tegra_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static const struct tegra_admaif_soc_data soc_data_tegra210 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .num_ch = TEGRA210_ADMAIF_CHANNEL_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .cmpnt = &tegra210_admaif_cmpnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .dais = tegra210_admaif_cmpnt_dais,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .regmap_conf = &tegra210_admaif_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .global_base = TEGRA210_ADMAIF_GLOBAL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .tx_base = TEGRA210_ADMAIF_TX_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .rx_base = TEGRA210_ADMAIF_RX_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static const struct tegra_admaif_soc_data soc_data_tegra186 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .num_ch = TEGRA186_ADMAIF_CHANNEL_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .cmpnt = &tegra186_admaif_cmpnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .dais = tegra186_admaif_cmpnt_dais,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .regmap_conf = &tegra186_admaif_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .global_base = TEGRA186_ADMAIF_GLOBAL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .tx_base = TEGRA186_ADMAIF_TX_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .rx_base = TEGRA186_ADMAIF_RX_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const struct of_device_id tegra_admaif_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) { .compatible = "nvidia,tegra210-admaif", .data = &soc_data_tegra210 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) { .compatible = "nvidia,tegra186-admaif", .data = &soc_data_tegra186 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) MODULE_DEVICE_TABLE(of, tegra_admaif_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int tegra_admaif_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct tegra_admaif *admaif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) admaif = devm_kzalloc(&pdev->dev, sizeof(*admaif), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (!admaif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) admaif->soc_data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dev_set_drvdata(&pdev->dev, admaif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) admaif->capture_dma_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) admaif->soc_data->num_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) sizeof(struct snd_dmaengine_dai_dma_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!admaif->capture_dma_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) admaif->playback_dma_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) admaif->soc_data->num_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) sizeof(struct snd_dmaengine_dai_dma_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (!admaif->playback_dma_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) for (i = 0; i < ADMAIF_PATHS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) admaif->mono_to_stereo[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) devm_kcalloc(&pdev->dev, admaif->soc_data->num_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) sizeof(unsigned int), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (!admaif->mono_to_stereo[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) admaif->stereo_to_mono[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) devm_kcalloc(&pdev->dev, admaif->soc_data->num_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) sizeof(unsigned int), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!admaif->stereo_to_mono[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) admaif->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) admaif->soc_data->regmap_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (IS_ERR(admaif->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_err(&pdev->dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return PTR_ERR(admaif->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) regcache_cache_only(admaif->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) regmap_update_bits(admaif->regmap, admaif->soc_data->global_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) TEGRA_ADMAIF_GLOBAL_ENABLE, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) for (i = 0; i < admaif->soc_data->num_ch; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) admaif->playback_dma_data[i].addr = res->start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) CH_TX_REG(TEGRA_ADMAIF_TX_FIFO_WRITE, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) admaif->capture_dma_data[i].addr = res->start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) CH_RX_REG(TEGRA_ADMAIF_RX_FIFO_READ, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) admaif->playback_dma_data[i].addr_width = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (of_property_read_string_index(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) "dma-names", (i * 2) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) &admaif->playback_dma_data[i].chan_name) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) "missing property nvidia,dma-names\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) admaif->capture_dma_data[i].addr_width = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (of_property_read_string_index(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "dma-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) (i * 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) &admaif->capture_dma_data[i].chan_name) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) "missing property nvidia,dma-names\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) err = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) admaif->soc_data->cmpnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) admaif->soc_data->dais,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) admaif->soc_data->num_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) "can't register ADMAIF component, err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static int tegra_admaif_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static const struct dev_pm_ops tegra_admaif_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) SET_RUNTIME_PM_OPS(tegra_admaif_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) tegra_admaif_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static struct platform_driver tegra_admaif_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .probe = tegra_admaif_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .remove = tegra_admaif_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .name = "tegra210-admaif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .of_match_table = tegra_admaif_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .pm = &tegra_admaif_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) module_platform_driver(tegra_admaif_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) MODULE_AUTHOR("Songhee Baek <sbaek@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) MODULE_DESCRIPTION("Tegra210 ASoC ADMAIF driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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