^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Stephen Warren <swarren@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011 - NVIDIA, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on code copyright/by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2008-2009, NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __TEGRA20_SPDIF_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __TEGRA20_SPDIF_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "tegra_pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Offsets from TEGRA20_SPDIF_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA20_SPDIF_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA20_SPDIF_STATUS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA20_SPDIF_STROBE_CTRL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA20_SPDIF_DATA_FIFO_CSR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA20_SPDIF_DATA_OUT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA20_SPDIF_DATA_IN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA20_SPDIF_CH_STA_RX_A 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA20_SPDIF_CH_STA_RX_B 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA20_SPDIF_CH_STA_RX_C 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA20_SPDIF_CH_STA_RX_D 0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA20_SPDIF_CH_STA_RX_E 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA20_SPDIF_CH_STA_RX_F 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA20_SPDIF_CH_STA_TX_A 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA20_SPDIF_CH_STA_TX_B 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA20_SPDIF_CH_STA_TX_C 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA20_SPDIF_CH_STA_TX_D 0x14C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA20_SPDIF_CH_STA_TX_E 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA20_SPDIF_CH_STA_TX_F 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA20_SPDIF_USR_STA_RX_A 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA20_SPDIF_USR_DAT_TX_A 0x1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Fields in TEGRA20_SPDIF_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Start capturing from 0=right, 1=left channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA20_SPDIF_CTRL_CAP_LC (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* SPDIF receiver(RX) enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA20_SPDIF_CTRL_RX_EN (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* SPDIF Transmitter(TX) enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA20_SPDIF_CTRL_TX_EN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Transmit Channel status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA20_SPDIF_CTRL_TC_EN (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Transmit user Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA20_SPDIF_CTRL_TU_EN (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Interrupt on transmit error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEGRA20_SPDIF_CTRL_IE_TXE (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Interrupt on receive error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEGRA20_SPDIF_CTRL_IE_RXE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Interrupt on invalid preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA20_SPDIF_CTRL_IE_P (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Interrupt on "B" preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA20_SPDIF_CTRL_IE_B (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Interrupt when block of channel status received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA20_SPDIF_CTRL_IE_C (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Interrupt when a valid information unit (IU) is received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA20_SPDIF_CTRL_IE_U (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Interrupt when RX user FIFO attention level is reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEGRA20_SPDIF_CTRL_QE_RU (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Interrupt when TX user FIFO attention level is reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TEGRA20_SPDIF_CTRL_QE_TU (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Interrupt when RX data FIFO attention level is reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TEGRA20_SPDIF_CTRL_QE_RX (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Interrupt when TX data FIFO attention level is reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TEGRA20_SPDIF_CTRL_QE_TX (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Loopback test mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TEGRA20_SPDIF_CTRL_LBK_EN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Pack data mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * 0 = Single data (16 bit needs to be padded to match the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * interface data bit size).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 1 = Packeted left/right channel data into a single word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TEGRA20_SPDIF_CTRL_PACK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * 00 = 16bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * 01 = 20bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * 10 = 24bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 11 = raw data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA20_SPDIF_BIT_MODE_16BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TEGRA20_SPDIF_BIT_MODE_20BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA20_SPDIF_BIT_MODE_24BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA20_SPDIF_BIT_MODE_RAW 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA20_SPDIF_CTRL_BIT_MODE_MASK (3 << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT (TEGRA20_SPDIF_BIT_MODE_16BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA20_SPDIF_CTRL_BIT_MODE_20BIT (TEGRA20_SPDIF_BIT_MODE_20BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA20_SPDIF_CTRL_BIT_MODE_24BIT (TEGRA20_SPDIF_BIT_MODE_24BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA20_SPDIF_CTRL_BIT_MODE_RAW (TEGRA20_SPDIF_BIT_MODE_RAW << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Fields in TEGRA20_SPDIF_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Note: IS_P, IS_B, IS_C, and IS_U are sticky bits. Software must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * write a 1 to the corresponding bit location to clear the status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Receiver(RX) shifter is busy receiving data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * This bit is asserted when the receiver first locked onto the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * preamble of the data stream after RX_EN is asserted. This bit is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * deasserted when either,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * (a) the end of a frame is reached after RX_EN is deeasserted, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * (b) the SPDIF data stream becomes inactive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA20_SPDIF_STATUS_RX_BSY (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Transmitter(TX) shifter is busy transmitting data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * This bit is asserted when TX_EN is asserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * This bit is deasserted when the end of a frame is reached after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * TX_EN is deasserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA20_SPDIF_STATUS_TX_BSY (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * TX is busy shifting out channel status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * This bit is asserted when both TX_EN and TC_EN are asserted and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * data from CH_STA_TX_A register is loaded into the internal shifter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * This bit is deasserted when either,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * (a) the end of a frame is reached after TX_EN is deasserted, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * (b) CH_STA_TX_F register is loaded into the internal shifter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TEGRA20_SPDIF_STATUS_TC_BSY (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * TX User data FIFO busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * This bit is asserted when TX_EN and TXU_EN are asserted and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * there's data in the TX user FIFO. This bit is deassert when either,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * (a) the end of a frame is reached after TX_EN is deasserted, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * (b) there's no data left in the TX user FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TEGRA20_SPDIF_STATUS_TU_BSY (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* TX FIFO Underrun error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TEGRA20_SPDIF_STATUS_TX_ERR (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* RX FIFO Overrun error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TEGRA20_SPDIF_STATUS_RX_ERR (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Preamble status: 0=Preamble OK, 1=bad/missing preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TEGRA20_SPDIF_STATUS_IS_P (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* B-preamble detection status: 0=not detected, 1=B-preamble detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TEGRA20_SPDIF_STATUS_IS_B (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * RX channel block data receive status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * 0=entire block not recieved yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * 1=received entire block of channel status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TEGRA20_SPDIF_STATUS_IS_C (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TEGRA20_SPDIF_STATUS_IS_U (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * RX User FIFO Status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * 1=attention level reached, 0=attention level not reached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TEGRA20_SPDIF_STATUS_QS_RU (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * TX User FIFO Status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * 1=attention level reached, 0=attention level not reached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEGRA20_SPDIF_STATUS_QS_TU (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * RX Data FIFO Status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * 1=attention level reached, 0=attention level not reached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TEGRA20_SPDIF_STATUS_QS_RX (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * TX Data FIFO Status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * 1=attention level reached, 0=attention level not reached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TEGRA20_SPDIF_STATUS_QS_TX (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Fields in TEGRA20_SPDIF_STROBE_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Indicates the approximate number of detected SPDIFIN clocks within a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * bi-phase period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_MASK (0xff << TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Data strobe mode: 0=Auto-locked 1=Manual locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TEGRA20_SPDIF_STROBE_CTRL_STROBE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Manual data strobe time within the bi-phase clock period (in terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * the number of over-sampling clocks).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_MASK (0x1f << TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Manual SPDIFIN bi-phase clock period (in terms of the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * over-sampling clocks).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK (0x3f << TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Fields in SPDIF_DATA_FIFO_CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Clear Receiver User FIFO (RX USR.FIFO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_CLR (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* RU FIFO attention level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU1_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) (TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU2_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) (TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU3_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) (TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU4_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) (TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Number of RX USR.FIFO levels with valid data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Clear Transmitter User FIFO (TX USR.FIFO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_CLR (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* TU FIFO attention level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU1_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) (TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU2_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) (TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU3_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) (TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU4_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) (TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Number of TX USR.FIFO levels that could be filled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Clear Receiver Data FIFO (RX DATA.FIFO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_CLR (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* RU FIFO attention level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU1_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) (TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU4_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) (TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU8_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) (TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU12_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) (TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Number of RX DATA.FIFO levels with valid data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Clear Transmitter Data FIFO (TX DATA.FIFO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_CLR (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* TU FIFO attention level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU1_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) (TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) (TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU8_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) (TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU12_WORD_FULL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) (TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Number of TX DATA.FIFO levels that could be filled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Fields in TEGRA20_SPDIF_DATA_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * This register has 5 different formats:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * 16-bit (BIT_MODE=00, PACK=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * 20-bit (BIT_MODE=01, PACK=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * 24-bit (BIT_MODE=10, PACK=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * raw (BIT_MODE=11, PACK=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * 16-bit packed (BIT_MODE=00, PACK=1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define TEGRA20_SPDIF_DATA_OUT_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define TEGRA20_SPDIF_DATA_OUT_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define TEGRA20_SPDIF_DATA_OUT_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_P (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_C (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_U (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_V (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Fields in TEGRA20_SPDIF_DATA_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * This register has 5 different formats:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * 16-bit (BIT_MODE=00, PACK=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * 20-bit (BIT_MODE=01, PACK=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * 24-bit (BIT_MODE=10, PACK=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * raw (BIT_MODE=11, PACK=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * 16-bit packed (BIT_MODE=00, PACK=1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Bits 31:24 are common to all modes except 16-bit packed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define TEGRA20_SPDIF_DATA_IN_DATA_P (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define TEGRA20_SPDIF_DATA_IN_DATA_C (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define TEGRA20_SPDIF_DATA_IN_DATA_U (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define TEGRA20_SPDIF_DATA_IN_DATA_V (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define TEGRA20_SPDIF_DATA_IN_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define TEGRA20_SPDIF_DATA_IN_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define TEGRA20_SPDIF_DATA_IN_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Fields in TEGRA20_SPDIF_CH_STA_RX_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Fields in TEGRA20_SPDIF_CH_STA_RX_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Fields in TEGRA20_SPDIF_CH_STA_RX_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Fields in TEGRA20_SPDIF_CH_STA_RX_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Fields in TEGRA20_SPDIF_CH_STA_RX_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Fields in TEGRA20_SPDIF_CH_STA_RX_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * The 6-word receive channel data page buffer holds a block (192 frames) of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * channel status information. The order of receive is from LSB to MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Fields in TEGRA20_SPDIF_CH_STA_TX_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Fields in TEGRA20_SPDIF_CH_STA_TX_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Fields in TEGRA20_SPDIF_CH_STA_TX_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Fields in TEGRA20_SPDIF_CH_STA_TX_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Fields in TEGRA20_SPDIF_CH_STA_TX_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Fields in TEGRA20_SPDIF_CH_STA_TX_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * The 6-word transmit channel data page buffer holds a block (192 frames) of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * channel status information. The order of transmission is from LSB to MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * bit, and from CH_STA_TX_A to CH_STA_TX_F then back to CH_STA_TX_A.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Fields in TEGRA20_SPDIF_USR_STA_RX_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * This 4-word deep FIFO receives user FIFO field information. The order of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * receive is from LSB to MSB bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Fields in TEGRA20_SPDIF_USR_DAT_TX_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * This 4-word deep FIFO transmits user FIFO field information. The order of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * transmission is from LSB to MSB bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct tegra20_spdif {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct clk *clk_spdif_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct snd_dmaengine_dai_dma_data capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct snd_dmaengine_dai_dma_data playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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