Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * tegra20_spdif.c - Tegra20 SPDIF driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Stephen Warren <swarren@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2011-2012 - NVIDIA, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "tegra20_spdif.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DRV_NAME "tegra20-spdif"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static int tegra20_spdif_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct tegra20_spdif *spdif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	clk_disable_unprepare(spdif->clk_spdif_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static int tegra20_spdif_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct tegra20_spdif *spdif = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	ret = clk_prepare_enable(spdif->clk_spdif_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		dev_err(dev, "clk_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 				struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 				struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct device *dev = dai->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	unsigned int mask = 0, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	int ret, spdifclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	mask |= TEGRA20_SPDIF_CTRL_PACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		val |= TEGRA20_SPDIF_CTRL_PACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		       TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	switch (params_rate(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		spdifclock = 4096000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		spdifclock = 5644800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		spdifclock = 6144000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		spdifclock = 11289600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		spdifclock = 12288000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	case 176400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		spdifclock = 22579200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		spdifclock = 24576000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		dev_err(dev, "Can't set SPDIF clock rate: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			   TEGRA20_SPDIF_CTRL_TX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			   TEGRA20_SPDIF_CTRL_TX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			   TEGRA20_SPDIF_CTRL_TX_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 				struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		tegra20_spdif_start_playback(spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		tegra20_spdif_stop_playback(spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int tegra20_spdif_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	dai->capture_dma_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	dai->playback_dma_data = &spdif->playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.hw_params	= tegra20_spdif_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.trigger	= tegra20_spdif_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct snd_soc_dai_driver tegra20_spdif_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.probe = tegra20_spdif_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.stream_name = "Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		.channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.ops = &tegra20_spdif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct snd_soc_component_driver tegra20_spdif_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static bool tegra20_spdif_wr_rd_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	case TEGRA20_SPDIF_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	case TEGRA20_SPDIF_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	case TEGRA20_SPDIF_STROBE_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	case TEGRA20_SPDIF_DATA_FIFO_CSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	case TEGRA20_SPDIF_DATA_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	case TEGRA20_SPDIF_DATA_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	case TEGRA20_SPDIF_CH_STA_RX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	case TEGRA20_SPDIF_CH_STA_RX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	case TEGRA20_SPDIF_CH_STA_RX_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	case TEGRA20_SPDIF_CH_STA_RX_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	case TEGRA20_SPDIF_CH_STA_RX_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	case TEGRA20_SPDIF_CH_STA_RX_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	case TEGRA20_SPDIF_CH_STA_TX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	case TEGRA20_SPDIF_CH_STA_TX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	case TEGRA20_SPDIF_CH_STA_TX_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	case TEGRA20_SPDIF_CH_STA_TX_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	case TEGRA20_SPDIF_CH_STA_TX_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	case TEGRA20_SPDIF_CH_STA_TX_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	case TEGRA20_SPDIF_USR_STA_RX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	case TEGRA20_SPDIF_USR_DAT_TX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static bool tegra20_spdif_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	case TEGRA20_SPDIF_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	case TEGRA20_SPDIF_DATA_FIFO_CSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	case TEGRA20_SPDIF_DATA_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	case TEGRA20_SPDIF_DATA_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	case TEGRA20_SPDIF_CH_STA_RX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	case TEGRA20_SPDIF_CH_STA_RX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	case TEGRA20_SPDIF_CH_STA_RX_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	case TEGRA20_SPDIF_CH_STA_RX_D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	case TEGRA20_SPDIF_CH_STA_RX_E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case TEGRA20_SPDIF_CH_STA_RX_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	case TEGRA20_SPDIF_USR_STA_RX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case TEGRA20_SPDIF_USR_DAT_TX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static bool tegra20_spdif_precious_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	case TEGRA20_SPDIF_DATA_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	case TEGRA20_SPDIF_DATA_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	case TEGRA20_SPDIF_USR_STA_RX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	case TEGRA20_SPDIF_USR_DAT_TX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct regmap_config tegra20_spdif_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.max_register = TEGRA20_SPDIF_USR_DAT_TX_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.writeable_reg = tegra20_spdif_wr_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.readable_reg = tegra20_spdif_wr_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.volatile_reg = tegra20_spdif_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.precious_reg = tegra20_spdif_precious_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int tegra20_spdif_platform_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct tegra20_spdif *spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct resource *mem, *dmareq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (!spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	dev_set_drvdata(&pdev->dev, spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	spdif->clk_spdif_out = devm_clk_get(&pdev->dev, "spdif_out");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (IS_ERR(spdif->clk_spdif_out)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		pr_err("Can't retrieve spdif clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		ret = PTR_ERR(spdif->clk_spdif_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	regs = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (!dmareq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		dev_err(&pdev->dev, "No DMA resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 					    &tegra20_spdif_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (IS_ERR(spdif->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		dev_err(&pdev->dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		ret = PTR_ERR(spdif->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	spdif->playback_dma_data.maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	spdif->playback_dma_data.slave_id = dmareq->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		ret = tegra20_spdif_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	ret = snd_soc_register_component(&pdev->dev, &tegra20_spdif_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 					 &tegra20_spdif_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	ret = tegra_pcm_platform_register(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		goto err_unregister_component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) err_unregister_component:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	snd_soc_unregister_component(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) err_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		tegra20_spdif_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int tegra20_spdif_platform_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		tegra20_spdif_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	tegra_pcm_platform_unregister(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	snd_soc_unregister_component(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct dev_pm_ops tegra20_spdif_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	SET_RUNTIME_PM_OPS(tegra20_spdif_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			   tegra20_spdif_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static struct platform_driver tegra20_spdif_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.pm = &tegra20_spdif_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	.probe = tegra20_spdif_platform_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	.remove = tegra20_spdif_platform_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) module_platform_driver(tegra20_spdif_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MODULE_ALIAS("platform:" DRV_NAME);