^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tegra20_i2s.h - Definitions for Tegra20 I2S driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Stephen Warren <swarren@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010,2012 - NVIDIA, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on code copyright/by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) 2009-2010, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Scott Peterson <speterson@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2010 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Iliyan Malchev <malchev@google.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef __TEGRA20_I2S_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define __TEGRA20_I2S_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "tegra_pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Register offsets from TEGRA20_I2S1_BASE and TEGRA20_I2S2_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA20_I2S_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA20_I2S_STATUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA20_I2S_TIMING 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA20_I2S_FIFO_SCR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA20_I2S_PCM_CTRL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA20_I2S_NW_CTRL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA20_I2S_TDM_CTRL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA20_I2S_TDM_TX_RX_CTRL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA20_I2S_FIFO1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA20_I2S_FIFO2 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Fields in TEGRA20_I2S_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA20_I2S_CTRL_FIFO2_TX_ENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA20_I2S_CTRL_FIFO1_ENABLE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA20_I2S_CTRL_FIFO2_ENABLE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA20_I2S_CTRL_FIFO1_RX_ENABLE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA20_I2S_CTRL_FIFO_LPBK_ENABLE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA20_I2S_CTRL_MASTER_ENABLE (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA20_I2S_LRCK_LEFT_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA20_I2S_LRCK_RIGHT_LOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA20_I2S_CTRL_LRCK_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA20_I2S_CTRL_LRCK_MASK (1 << TEGRA20_I2S_CTRL_LRCK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA20_I2S_CTRL_LRCK_L_LOW (TEGRA20_I2S_LRCK_LEFT_LOW << TEGRA20_I2S_CTRL_LRCK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEGRA20_I2S_CTRL_LRCK_R_LOW (TEGRA20_I2S_LRCK_RIGHT_LOW << TEGRA20_I2S_CTRL_LRCK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA20_I2S_BIT_FORMAT_I2S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA20_I2S_BIT_FORMAT_RJM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA20_I2S_BIT_FORMAT_LJM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA20_I2S_BIT_FORMAT_DSP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEGRA20_I2S_CTRL_BIT_FORMAT_MASK (3 << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEGRA20_I2S_CTRL_BIT_FORMAT_I2S (TEGRA20_I2S_BIT_FORMAT_I2S << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TEGRA20_I2S_CTRL_BIT_FORMAT_RJM (TEGRA20_I2S_BIT_FORMAT_RJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEGRA20_I2S_CTRL_BIT_FORMAT_LJM (TEGRA20_I2S_BIT_FORMAT_LJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA20_I2S_CTRL_BIT_FORMAT_DSP (TEGRA20_I2S_BIT_FORMAT_DSP << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA20_I2S_BIT_SIZE_16 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA20_I2S_BIT_SIZE_20 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TEGRA20_I2S_BIT_SIZE_24 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA20_I2S_BIT_SIZE_32 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA20_I2S_CTRL_BIT_SIZE_MASK (3 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TEGRA20_I2S_CTRL_BIT_SIZE_16 (TEGRA20_I2S_BIT_SIZE_16 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TEGRA20_I2S_CTRL_BIT_SIZE_20 (TEGRA20_I2S_BIT_SIZE_20 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA20_I2S_CTRL_BIT_SIZE_24 (TEGRA20_I2S_BIT_SIZE_24 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEGRA20_I2S_CTRL_BIT_SIZE_32 (TEGRA20_I2S_BIT_SIZE_32 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEGRA20_I2S_FIFO_16_LSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TEGRA20_I2S_FIFO_20_LSB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TEGRA20_I2S_FIFO_24_LSB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TEGRA20_I2S_FIFO_32 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TEGRA20_I2S_FIFO_PACKED 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK (7 << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TEGRA20_I2S_CTRL_FIFO_FORMAT_16_LSB (TEGRA20_I2S_FIFO_16_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TEGRA20_I2S_CTRL_FIFO_FORMAT_20_LSB (TEGRA20_I2S_FIFO_20_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TEGRA20_I2S_CTRL_FIFO_FORMAT_24_LSB (TEGRA20_I2S_FIFO_24_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TEGRA20_I2S_CTRL_FIFO_FORMAT_32 (TEGRA20_I2S_FIFO_32 << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED (TEGRA20_I2S_FIFO_PACKED << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TEGRA20_I2S_CTRL_IE_FIFO1_ERR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TEGRA20_I2S_CTRL_IE_FIFO2_ERR (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TEGRA20_I2S_CTRL_QE_FIFO1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TEGRA20_I2S_CTRL_QE_FIFO2 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Fields in TEGRA20_I2S_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TEGRA20_I2S_STATUS_FIFO1_RDY (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TEGRA20_I2S_STATUS_FIFO2_RDY (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TEGRA20_I2S_STATUS_FIFO1_BSY (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA20_I2S_STATUS_FIFO2_BSY (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA20_I2S_STATUS_FIFO1_ERR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA20_I2S_STATUS_FIFO2_ERR (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA20_I2S_STATUS_QS_FIFO1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA20_I2S_STATUS_QS_FIFO2 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Fields in TEGRA20_I2S_TIMING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA20_I2S_TIMING_NON_SYM_ENABLE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK (TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Fields in TEGRA20_I2S_FIFO_SCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA20_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA20_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TEGRA20_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TEGRA20_I2S_FIFO_SCR_FIFO2_CLR (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TEGRA20_I2S_FIFO_SCR_FIFO1_CLR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK (3 << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT (TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK (3 << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT (TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct tegra20_i2s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct snd_soc_dai_driver dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk *clk_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct snd_dmaengine_dai_dma_data capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct snd_dmaengine_dai_dma_data playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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